––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––– ■ ML53612 ■
Configuration Register Byte 4, AR = 0004h
DR_0
[2:0]
3
C
[34:32]
35
Definition
Master PLL Mode [2:0]
Reserved
[5:4]
6
[37:36]
38
Master PLL Mode Read-back [1:0]
Condition Master PLL Reference
Reserved
7
39
[1]
Master PLL Mode [2:0] (C_ [34:32]) (Read/Write)
000
001
010
011
100
101
110
111
→
→
→
→
→
→
→
→
Normal (Default)
Reserved
Holdover
Free Run
Reserved
Reserved
Auto Normal to Holdover switch on Master PLL error
Auto Normal to Free Run switch on Master PLL error
1. Master PLL error occurs when the Master PLL is out of lock with its reference signal. It is necessary to manually select "Normal" to go back to
normal operation after an auto switch has occurred.
Master PLL Mode Read-back [1:0] (C_ [37:36]) (Read Only)
00
01
10
11
→
→
→
→
Normal
Reserved
Holdover
Free Run
Condition Master PLL Reference (C_ [38]) (Read/Write)
When enabled, conditions a change in references for MTIE compatibility.
0
1
→
→
Condition Master PLL Reference Disabled (Default)
Condition Master PLL Reference Enabled
Oki Semiconductor
21
OKI [ OKI ELECTRONIC COMPONETS ]
