■ ML53612 ■ ––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
5.4 Configuration Registers
Note: All "Reserved" configuration registers should be written "0".
Configuration Register Byte 0, AR = 0000h
DR_0
C
0
Definition
0
1
Diagnostic Mode
1
Test Mode
2
2
APLL Power-down Mode
APLL Bypass Mode
APLL CLKREF Frequency [3:0]
3
3
[7:4]
[7:4]
Diagnostic Mode (C_ [0]) (Read/Write)
Set to 0 for normal operation
0
1
→
→
Diagnostic Mode Disabled
Diagnostic Mode Enabled (Default)
Test Mode (C_ [1]) (Read/Write)
Enables testing with the slave DPLL bypassed. Set to 0 for normal operation.
0
1
→
→
Test Mode Disabled (Default)
Test Mode Enabled
APLL Power-down Mode (C_ [2]) (Read/Write)
Powers down analog PLL, resets APLL charge pump. Set to 0 for normal operation.
0
1
→
→
APLL Power-down Mode Disabled
APLL Power-down Mode Enabled (Default)
APLL Bypass Mode (C_ [3]) (Read/Write)
APLL Bypass used during simulation and testing. Set to 0 for normal operation.
0
1
→
→
APLL Bypass Mode Disabled
APLL Bypass Mode Enabled (Default)
16
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