NXP Semiconductors
PF4210
14-channel power management integrated circuit (PMIC) for audio/video applications
Table 25.ꢀPWRON hardware debounce bit settings
Bits
State [1] Turn on
debounce (ms)
0.0
Falling edge INT
debounce (ms)
Rising edge INT
debounce (ms)
PWRONDBNC[1:0] 00
31.25
31.25
125
31.25
31.25
31.25
31.25
01
10
11
31.25
125
750
750
[1] The sense bit, PWRONS is not debounced and follows the state of the PWRON pin.
10.4.2.2 Turn off events
10.4.2.2.1 PWRON pin
The PWRON pin is used to power off the PF4210. The PWRON pin can be configured
with OTP to power off the PMIC under the following two conditions:
1. PWRON_CFG bit = 0, SWxOMODE bit = 0 and PWRON pin is low
2. PWRON_CFG bit = 1, SWxOMODE bit = 0, PWRONRSTEN = 1 and PWRON is held
low for longer than 4.0 seconds. Alternatively, the system can be configured to restart
automatically by setting the RESTARTEN bit.
10.4.2.2.2 Thermal protection
If the die temperature surpasses a given threshold, the thermal protection circuit powers
off the PMIC to avoid damage. A turn on event does not power on the PMIC while it is in
thermal protection.
The part remains in off mode until the die temperature decreases below a given
threshold. There are no specific interrupts related to this other than the warning interrupt.
See Section 8.3 "Power dissipation" for more information.
10.4.2.2.3 Undervoltage detection
When the voltage at VIN drops below the undervoltage falling threshold UVDET, the
state machine transitions to the coin cell mode.
10.4.3 Power tree
The PF4210 PMIC features up to six buck regulators, one boost regulator, six general
purpose LDOs, one switch/LDO combination, and a DDR voltage reference to supply
voltages for the application processor and peripheral devices. The buck regulators as
well as the boost regulator are supplied directly from the main input supply (VIN). The
inputs to all of the buck regulators must be tied to VIN, whether they are powered on or
off.
The six general use LDO regulators are directly supplied from the main input supply
or from the switching regulators depending on the application requirements. Since
VREFDDR is intended to provide DDR memory reference voltage, it is supplied by any
rail supplying voltage to DDR memories; the typical application recommends the use
of SW3 as the input supply for VREFDDR. VSNVS is supplied by either the main input
supply or the coin cell. See Table 26 for a summary of all power supplies provided by the
PF4210.
PF4210
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2018. All rights reserved.
Data sheet: technical data
Rev. 2.0 — 14 November 2018
30 / 137
NXP [ NXP ]
