NXP Semiconductors
PF4210
14-channel power management integrated circuit (PMIC) for audio/video applications
In the sleep mode, the regulator uses the set point as programmed by SW1xOFF[5:0] for
SW1A/B/C and by SWxOFF[6:0] for SW2, SW3A/B, and SW4. The activated regulators
maintain settings for this mode and voltage until the next turn on event. Table 23 shows
the control bits in sleep mode. During sleep mode, interrupts are active and the INTB pin
reports any unmasked fault event.
Table 23.ꢀRegulator mode control
SWxOMODE
Off operational mode (sleep) [1]
0
1
Off
PFM
[1] For sleep mode, an activated switching regulator should use the off mode set point as programmed by SW1xOFF[5:0] for
SW1A/B/C and SWxOFF[6:0] for SW2, SW3A/B, and SW4.
10.4.1.5 Coin cell mode
In the coin cell state, the coin cell is the only valid power source (VIN = 0.0 V) to the
PMIC. No turn on event is accepted in the coin cell state. Transition to the off state
requires VIN surpasses UVDET threshold. RESETBMCU is held low in this mode.
If the coin cell is depleted, a complete system reset occurs. At the next application of
power and the detection of a turn on event, the system is re-initialized with all I2C bits
including those reset on COINPORB, which are restored to their default states.
10.4.2 State machine flow summary
Table 24 provides a summary matrix of the PF4210 flow diagram to show the conditions
needed to transition from one state to another.
Table 24.ꢀState machine flow summary
STATE
Next state
OFF
Coin cell
Sleep
Standby
ON
Initial OFF
state
X
VIN < UVDET
X
X
PWRON_CFG = 0
PWRON = 1 & VIN
UVDET
>
or
PWRON_CFG = 1
PWRON = 0 < 4.0 s
& VIN > UNDET
Coin cell
Sleep
VIN > UVDET
X
X
X
X
X
X
Thermal shutdown
VIN < UVDET
PWRON_CFG = 0
PWRON = 1 & VIN
UVDET
>
PWRON_CFG = 1
PWRON = 0 ≥ 4.0 s
or
Any SWxOMODE = 1
&
PWRON_CFG = 1
PWRON = 0 < 4.0 s &
VIN > UNDET
PWRONRSTEN = 1
PF4210
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© NXP B.V. 2018. All rights reserved.
Data sheet: technical data
Rev. 2.0 — 14 November 2018
28 / 137
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