NXP Semiconductors
PF4210
14-channel power management integrated circuit (PMIC) for audio/video applications
STATE
Next state
OFF
Coin cell
Sleep
Standby
ON
Standby
Thermal shutdown
VIN < UVDET
PWRON_CFG = 0
PWRON = 0
X
Standby deasserted
PWRON_CFG = 0
PWRON = 0
Any SWxOMODE = 1
or
All SWxOMODE = 0
or
PWRON_CFG = 1
PWRON = 0 ≥ 4.0 s
PWRON_CFG = 1
PWRON = 0 ≥ 4.0 s
All SWxOMODE = 0 &
PWRONRSTEN = 1
Any SWxOMODE = 1
&
PWRONRSTEN = 1
ON
Thermal shutdown
VIN < UVDET
PWRON_CFG = 0
PWRON = 0
Standby
asserted
X
PWRON_CFG = 0
PWRON = 0
Any SWxOMODE = 1
or
All SWxOMODE = 0
or
PWRON_CFG = 1
PWRON = 0 ≥ 4.0 s
PWRON_CFG = 1
PWRON = 0 ≥ 4.0 s
All SWxOMODE = 0 &
PWRONRSTEN = 1
Any SWxOMODE = 1
&
PWRONRSTEN = 1
10.4.2.1 Turn on events
From off and sleep modes, the PMIC is powered on by a turn on event. The type of
turn on event depends on the configuration of PWRON. PWRON may be configured as
an active high when PWRON_CFG = 0, or as the input of a mechanical switch when
PWRON_CFG = 1. VIN must be greater than UVDET for the PMIC to turn on.
When PWRON is configured as an active high and PWRON is high (pulled up to VSNVS)
before VIN is valid, a VIN transition from 0.0 V to a voltage greater than UVDET is also a
turn on event. See Figure 7 and the Table 24 for more details. Any regulator enabled in
the sleep mode remains enabled when transitioning from sleep to on, the regulator does
not turn off and then on again to match the startup sequence. Detailed description of the
PWRON configurations are as follows:
• If PWRON_CFG = 0, the PWRON signal is high and VIN > UVDET, the PMIC turns on;
the interrupt and sense bits, PWRONI and PWRONS respectively are set
• If PWRON_CFG = 1, VIN > UVDET and PWRON transitions from high to low, the PMIC
turns on; the interrupt and sense bits, PWRONI and PWRONS respectively are set
The sense bit shows the real time status of the PWRON pin. In this configuration,
the PWRON input can be a mechanical switch debounced through a programmable
debouncer, PWRONDBNC[1:0], to avoid a response to a very short (unintentional) key
press. The interrupt is generated for both the falling and the rising edge of the PWRON
pin. By default, a 30 ms interrupt debounce is applied to both falling and rising edges.
The falling edge debounce timing can be extended with PWRONDBNC[1:0] as defined in
Table 25. The interrupt is cleared by software, or when cycling through the off mode.
PF4210
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2018. All rights reserved.
Data sheet: technical data
Rev. 2.0 — 14 November 2018
29 / 137
NXP [ NXP ]
