NXP Semiconductors
PF4210
14-channel power management integrated circuit (PMIC) for audio/video applications
A product may be designed to go into a low-power mode after periods of inactivity. The
STANDBY pin is provided for board level control of going in and out of such Deep Sleep
Modes (DSM).
When a product is in DSM, it may be able to reduce the overall platform current by
lowering the regulator output voltage, changing the operating mode of the regulators
or disabling some regulators. The configuration of the regulators in standby is
preprogrammed through the I2C interface.
Note that the STANDBY pin is programmable for active high or active low polarity, and
decoding of a standby event takes into account the programmed input polarity as shown
in Table 21. When the PF4210 is powered up first, regulator settings for the standby
mode are mirrored from the regulator settings for the on mode. To change the STANDBY
pin polarity to active low, set the STANDBYINV bit via software first, and then change the
regulator settings for standby mode as required. For simplicity, STANDBY generally is
referred to as active high throughout this document.
Table 21.ꢀStandby pin and polarity control
STANDBY (pin) [1]
STANDBYINV (I2C bit) [2]
STANDBY control [3]
0
0
1
1
0
1
0
1
0
1
1
0
[1] The state of the STANDBY pin only has influence in on mode.
[2] Bit 6 in power control register (ADDR – 0x1B)
[3] STANDBY = 0: system is not in standby, STANDBY = 1: system is in standby
Since STANDBY pin activity is driven asynchronously to the system, a finite time
is required for the internal logic to qualify and respond to the pin level changes. A
programmable delay is provided to hold off the system response to a standby event. This
allows the processor and peripherals some time after a standby instruction has been
received to terminate processes to facilitate seamless entering into standby mode.
When enabled (STBYDLY = 01, 10, or 11) per Table 22, STBYDLY delays the standby
initiated response for the entire IC, until the STBYDLY counter expires.
An allowance should be made for three additional 32 kHz cycles required to synchronize
the standby event.
Table 22.ꢀSTANDBY delay – initiated response
STBYDLY[1:0] [1]
Function
00
01
10
11
No delay
One 32 kHz period (default)
Two 32 kHz periods
Three 32 kHz periods
[1] Bits [5:4] in power control register (ADDR – 0x1B)
10.4.1.4 Sleep mode
• Depending on PWRON pin configuration, sleep mode is entered when PWRON is
deasserted and SWxOMODE bit is set.
• To exit sleep mode, assert the PWRON pin.
PF4210
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© NXP B.V. 2018. All rights reserved.
Data sheet: technical data
Rev. 2.0 — 14 November 2018
27 / 137
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