NXP Semiconductors
FXPS7115D4
Digital absolute pressure sensor, 40 kPa to 115 kPa
Table 44.ꢀDEVLOCK_WR - lock register writes register (address 10h) bit description
Bit
Symbol
Description
7
ENDINIT
The ENDINIT bit is a control bit used to indicate that the user has completed all device and
system level initialization tests. Once the ENDINIT bit is set, writes to all writable register bits
are inhibited except for the DEVLOCK_WR register. Once set, the ENDINIT bit can only be
cleared by a device reset.
When ENDINIT is set, the following occurs:
• An error detection is enabled for all user writable registers. The error detection code is
continuously calculated on the user writable registers and verified against a previously
calculated error detection code.
• Self-test is disabled and inhibited.
• Register writes are inhibited with the exception of the RESET[1:0] bits in the DEVLOCK_WR
register.
3
SUP_ERR_DIS
The supply error disable bit allows the user to disable reporting of the supply errors in the SPI
status fields.
1 to 0 RESET[1:0]
To reset the device, three consecutive register write operations must be performed in the
order shown in Table 45, or the device will not reset.
The response to a register write returns the new register value, including the values written
to the RESET[1:0] bits. After the third register write command, the device initiates a reset
and thus does not transmit an acknowledge. The response to a register read returns '00' for
RESET[1:0] and terminates the reset sequence. The reset control bits are not included in the
read/write array error detection.
Table 45.ꢀDevice reset command sequence
Register write to DEVLOCK_WR
Register write 1
RESET[0]
RESET[1]
Effect
0
1
0
0
1
1
No effect
No effect
Device RESET
Register write 2
Register write 3
7.7.5 UF_REGION_W, UF_REGION_R - UF region selection registers (address
14h, 15h)
The UF region load register is a user read/write register that contains the control bits for
the UF0 and UF1 regions to be accessed. This register is included in the user read/write
array error detection. The UF region active register is a read-only register that contains
the status bits for the UF0 and UF1 regions to be accessed. This register is included in
the user read/write array error detection.
The UF_REGION_W register is readable and writable in SPI mode or I2C mode. The
UF_REGION_R register is readable in SPI mode or I2C mode.
Table 46.ꢀUF_REGION_W - UF region selection register (address 14h) bit allocation
Bit
7
6
5
4
3
2
0
1
0
0
0
Symbol
Factory default
Access
REGION_LOAD[3:0]
0
1
1
1
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
FXPS7115D4
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© NXP B.V. 2019. All rights reserved.
Product data sheet
Rev. 3 — 5 December 2019
36 / 72
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