NXP Semiconductors
FXPS7115D4
Digital absolute pressure sensor, 40 kPa to 115 kPa
Table 37.ꢀDEVSTAT1 - device status register (address 02h) bit description
Bit
Symbol
Description
7
VCCUV_ERR
The VCC undervoltage error bit is set if the VCC voltage falls below the voltage specified in
Table 101. See Section 7.1 for details on the VCC undervoltage monitor. This bit is cleared
once sensor data is valid for read through one of the device communication interfaces
(tPOR_DataValid).
0 — No error detected
1 — VCC voltage low
5
VCCOV_ERR
The VCC overvoltage error bit is set if the VCC voltage rises above the voltage specified in
Table 101. See Section 7.1 for details on the VCC overvoltage monitor. A common timer is
used for all error bits in the DEVSTAT1 register. If any supply error is present, the timer is
reset to tUVOV_RCV. This bit is cleared once sensor data is valid for read through one of the
device communication interfaces (tPOR_DataValid).
0 — No error detected
1 — VCC voltage high
3
2
1
0
INTREGA_ERR
INTREG_ERR
INTREGF_ERR
CONT_ERR
The internal analog regulator voltage out-of-range error bit is set if the internal analog
regulator voltage falls outside of expected limits. This bit is cleared once sensor data is valid
for read through one of the device communication interfaces (tPOR_DataValid).
0 — No error detected
1 — Internal analog regulator voltage out of range
The internal digital regulator voltage out-of-range error bit is set if the internal digital regulator
voltage falls outside of expected limits. This bit is cleared once sensor data is valid for read
through one of the device communication interfaces (tPOR_DataValid).
0 — No error detected
1 — Internal digital regulator voltage out of range
The internal OTP regulator voltage out-of-range error bit is set if the internal OTP regulator
voltage falls outside of expected limits. This bit is cleared once sensor data is valid for read
through one of the device communication interfaces (tPOR_DataValid).
0 — No error detected
1 — Internal OTP regulator voltage out of range
The continuity monitor passes a low current through a connection around the perimeter of
the device and monitors the continuity of the connection. The error bit is set if a discontinuity
is detected in the connection. A common timer is used for all error bits in the DEVSTAT1
register. If any supply error is present, the timer is reset to tUVOV_RCV. This bit is cleared
based on the state of the SUP_ERR_DIS bit in the DEVLOCK_WR register as shown in
Section 7.7.4.
0 — No error detected
1 — Error detected in the continuity of the edge seal monitor circuit
7.7.2.3 DEVSTAT2 - device status register (address 03h)
Table 38.ꢀDEVSTAT2 - device status register (address 03h) bit allocation
Bit
7
6
5
4
3
2
1
0
Symbol
F_OTP_
ERR
U_OTP_
ERR
U_RW_ERR
U_W_
ACTIVE
reserved
TEMP0_
ERR
reserved
reserved
Reset
0
0
0
0
reserved
R
0
reserved
R
reserved
R
Access
R
R
R
R
R
FXPS7115D4
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© NXP B.V. 2019. All rights reserved.
Product data sheet
Rev. 3 — 5 December 2019
33 / 72
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