NXP Semiconductors
FXPS7115D4
Digital absolute pressure sensor, 40 kPa to 115 kPa
Table 52.ꢀSOURCEID_0 - source identification register (address 1Ah) bit allocation
Bit
7
SID0_EN
0
6
reserved
0
5
reserved
0
4
reserved
0
3
2
1
0
Symbol
Factory default
Access
SOURCEID_0[3:0]
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Table 53.ꢀSOURCEID_1 - source identification register (address 1Bh) bit allocation
Bit
7
SID1_EN
0
6
reserved
0
5
reserved
0
4
reserved
0
3
2
1
0
Symbol
Factory default
Access
SOURCEID_1[3:0]
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
7.7.8 TIMING_CFG - communication timing register (address 22h)
The communication timing configuration register is a user programmed read/write
register that contains user-specific configuration information for protocol timing. This
register is included in the read/write array error detection. This register is readable and
writable in SPI mode or I2C mode.
Table 54.ꢀTIMING_CFG - communication timing register (address 22h) bit allocation
Bit
7
6
5
4
3
2
1
0
Symbol
reserved
OSCTRAIN_
SEL
CK_CAL_
RST
reserved
reserved
CK_CAL_EN
Factory default
Access
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
7.7.9 SPI Configuration Control Register (SPI_CFG, Address 3Dh)
In SPI mode, the SPI configuration control register is a user programmed read/write
register that contains the SPI protocol configuration information. This register is included
in the read/write array error detection. This register is readable and writable in SPI mode
or I2C mode
Table 55.ꢀSPI_CFG Register (address 3Dh) bit allocation
Bit
7
reserved
0
6
DATASIZE
0
5
4
3
2
1
0
Symbol
Factory default
Access
SPI_CRC_LEN[1:0]
SPICRCSEED[3:0]
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
7.7.9.1 SPI Data Field Size (DATASIZE)
The SPI data field size bit controls the size of the SPI data field as shown in Table 56.
Table 56.ꢀDATASIZE Bit Definition
DATASIZE
SPI Data Field Size
12-Bits
0
1
16-Bits
FXPS7115D4
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© NXP B.V. 2019. All rights reserved.
Product data sheet
Rev. 3 — 5 December 2019
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