NXP Semiconductors
FXPS7115D4
Digital absolute pressure sensor, 40 kPa to 115 kPa
5. Repeat steps 1 through 4 for the next desired UF region to read.
Notes:
• The user must take care to ensure that the desired registers are addressed. For
example, if the REGION_LOAD bits are set to Ah and the user executes a read of
address $C2, the contents of registers $A2 will be transmitted. No error detection is
included other than a read of the REGION_ACTIVE bits.
• For COMMTYPE options with multiple protocol options (COMMTYPE = '000' or '001'),
no error detection is included other than a read of the REGION_ACTIVE bits. The user
must take care to ensure that the REGION_LOAD bits are not inadvertently changed
by an alternative protocol while executing register reads.
• In SPI and I2C modes, once the ENDINIT bit is set, writes to registers other than the
RESET[1:0] bits are inhibited. For this reason, reads of the UF0, UF1, and F registers
will only be possible for the region selected by the REGION_ACTIVE bits at the time
ENDINIT is set.
7.7.6 COMMTYPE - communication type register (address 16h)
When writing to this register, care must be taken to prevent from inadvertently disabling
the desired communication mode. Communication mode register value changes, that
disable a protocol, including writes to OTP, will not take effect until a device reset occurs
to prevent disabling a necessary communication method.
Table 50.ꢀCOMMTYPE - communication type register (address 16h) bit allocation
Bit
7
reserved
R/W
6
reserved
R/W
5
reserved
R/W
4
reserved
R/W
3
reserved
R/W
2
1
0
Symbol
Access
Reset
COMMTYPE[2:0]
R/W
0
R/W
0
R/W
0
0
0
0
0
0
Table 51.ꢀCOMMTYPE - communication type register (address 16h) bit description
Bit
Symbol
Description
2 to 0
COMMTYPE[2:0}
Communication protocol selection
000
001
010
011
100
101
110
111
32-bit SPI (no internal self-test, debug mode)
32-bit SPI (with startup internal self-test)
32-bit SPI (no internal self-test, debug mode)
reserved
32-bit SPI (no internal self-test, debug mode)
reserved
I2C (pin 3 acts as an Interrupt)
I2C (pin 3 acts as an interrupt)
7.7.7 SOURCEID_x - source identification registers (address 1Ah, 1Bh)
The source identification registers are user programmed read/write registers that contain
the source identification information used in SPI Mode. These registers are included in
the read/write array error detection. These registers are readable and writable in SPI
mode or I2C mode.
FXPS7115D4
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© NXP B.V. 2019. All rights reserved.
Product data sheet
Rev. 3 — 5 December 2019
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