NXP Semiconductors
FXTH87E
FXTH87E, Family of Tire Pressure Monitor Sensors
Jump Table
Vector Vector
Vector Module
Name Source
Vector Addr
(High/Low)
Flags
Enables Description
Priority
No.
2
$DFFA - $DFFB
$DFFC - $DFFD
Reserved
SWI
Vswi
Interrupt from the CPU when an SWI
instruction has been executed.
1
—
—
—
—
opcode
Sys Ctrl
- POR
Reset from power on sequence.
Sys Ctrl
- PRF
Reset from PWU when the reset interval
elapsed.
PRF
—
PRST[5:0]
COPE
Sys Ctrl
- COP
Reset when COP watchdog times out.
Reset from the LVD when the supply
voltage
Sys Ctrl
Vreset
0
$DFFE -$DFFF
—
LVDRE
- LVD
has dropped below the LVD threshold.
Temp
Restart
Reset when the temperature falls below
the temperature restart threshold
—
—
—
TRE
—
Illegal
opcode
Reset from the CPU when trying to
execute an illegal opcode.
Illegal
address
Reset from the CPU when trying to
access an illegal address.
—
7.6 Low-Voltage Detect (LVD) System
The FXTH87E includes a system to detect low voltage conditions in order to protect
memory contents and control MCU system states during supply voltage variations. The
system is comprised of a power-on reset (POR) circuit and an LVD circuit with a user
selectable trip voltage, either high (VLVDH) or low (VLVDL). The LVD circuit is enabled
when LVDE in SPMSC1 is high and the trip voltage is selected by LVDV in SPMSC3.
The LVD is disabled upon entering any of the STOP modes unless the LVDSE bit is set.
If LVDSE and LVDE are both set, then the MCU cannot enter STOP1.
7.6.1 Power-on reset operation
When power is initially applied to the FXTH87E, or when the supply voltage drops
below the VPOR level, the POR circuit will cause a reset condition. As the supply voltage
rises, the LVD circuit will hold the chip in reset until the supply has risen above the level
determined by LVDV bit. Both the POR bit and the LVD bit in SRS are set following a
POR.
7.6.2 LVD reset operation
The LVD can be configured to generate a reset upon detection of a low voltage condition
has occurred by setting LVDRE to 1 when the supply voltage has fallen below the level
determined by LVDV bit. After an LVD reset has occurred, the LVD system will hold the
FXTH87E in reset until the supply voltage has risen above the level determined by LVDV
bit. The threshold for falling and rising differ by a small amount of hysteresis. The LVD bit
in the SRS register is set following either an LVD reset or POR.
FXTH87ERM
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© NXP B.V. 2019. All rights reserved.
Reference manual
Rev. 5.0 — 4 February 2019
41 / 183
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