NXP Semiconductors
FXTH87E
FXTH87E, Family of Tire Pressure Monitor Sensors
15.17 PLL control registers A - PLLCR[1:0], RPAGE = 0
The PLLCR[1:0] registers contain 16 control bits for the RFM as described in Table 150
and Table 151. These bits are only accessible when the RPAGE bit is cleared.
Table 150.ꢀPLL control registers A (PLLCR[1:0], RPAGE = 0) (address ($0038)
Bit
R
7
6
5
4
3
2
1
0
AFREQ[12:5]
W
Reset
0
0
0
0
0
0
0
0
Table 151.ꢀPLL control registers A (PLLCR[1:0], RPAGE = 0) (address ($0039)
Bit
R
7
6
5
4
3
2
POL
0
1
0
AFREQ[4:0]
0
CODE
W
Reset
0
0
0
0
0
0
Table 152.ꢀPLLCR[1:0] field descriptions
Field
Description
PLL Divider Ratio A — The AFREQ[12:0] control bits select the PLL divider ratio for a data zero in the
FSK mode of modulation as described by the following equation:
where:
AFREQ[12:0]
(PLLCR0[7:0],
PLLCR1[7:3])
fDATA0 = RF Carrier frequency for a data zero in MHz
fXTAL = External crystal frequency in MHz, 26 MHz
CF = State of the CF carrier select bit
AFREQ = Decimal value of the AFREQ[12:0] binary weighted bits
The AFREQ[12:0] control bits are cleared by the RFMRST signal. 1 LSB of AFREQ[12:0] = 3.17 kHz.
Data Polarity — The POL control bit selects the polarity of the data encoding selected by the
CODE[1:0] bits. The POL control bit is cleared by the RFMRST signal.
2
0ꢀNRZ and MCU direct DATA bit data non-inverted and Manchester encoding polarity as in Figure 42
and Bi-Phase encoding polarity as in Figure 44.
POL
1ꢀNRZ and MCU direct DATA bit data inverted and Manchester encoding polarity as in Figure 43 and
Bi-Phase encoding polarity as in Figure 45.
Data Encoding and Source — The CODE[1:0] control bits select the type of data encoding and
source of data for the RF output.
The CODE[1:0] control bits are cleared by the RFMRST signal.
00ꢀManchester encoded data from the RFM data buffer.
01ꢀBi-Phase encoded data from the RFM data buffer.
1:0
CODE[1:0]
10ꢀNRZ direct data from the RFM data buffer (can be mixed NRZ and Manchester at 2X the data
rate).
11ꢀMCU direct mode with RF output driven by the state of the DATA bit.
FXTH87ERM
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Reference manual
Rev. 5.0 — 4 February 2019
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