NXP Semiconductors
FXTH87E
FXTH87E, Family of Tire Pressure Monitor Sensors
Field
Description
Interframe Interrupt Delay — The IFID control bit selects when the RFIF bit is set and the MCU is
interrupted. The IFID control bit is cleared by the RFMRST signal.
4
0ꢀThe RFIF bit is set and the MCU interrupted if the RFIEN bit is set, after the last frame transmitted.
IFID
1ꢀThe RFIF bit is set and the MCU interrupted if the RFIEN bit is set, only after the last frame plus an
additional interframe message is transmitted.
3-0
FNUM
[3:0]
FNUM[3:0] — The FNUM[3:0] bits set the number of frames transmitted in each RF datagram. The frames
will be randomly spaced apart as described in Section 15.3 "Transmission randomization".These bits are
cleared by an RFM reset. The number of frame transmitted is the binary number plus one.
15.13 RFM control register 4 — RFCR4
The RFCR4 register contains eight control bits to set the initial and interframe timing
base timing variable as described in Table 142. A RFMRST signal clears the RFBT[7:0]
bits.
Table 142.ꢀRFCR4 register — base time variable (address $0034)
Bit
R
7
6
5
4
3
2
1
0
RFBT[7:0]
W
Reset
1
0
0
0
0
0
0
0
Table 143.ꢀRFCR4 field descriptions
Field
Description
Base Timer — The RFBT[7:0] control bits select the interframe timing between multiple frames of
7:0
RFBT
[7:0]
transmission. The base time\ value is equal to a nominal one millisecond for each count of the RFBT[7:0]
bits. The RFBT[7:0] control bits are cleared by the RFMRST signal and must be set to either 0 or between 5
and 255.
15.14 RFM control register 5 — RFCR5
The RFCR5 register contains eight control bits to set the initial and interframe random
timing variable as described in Table 144. A RFMRST signal clears the LFSR[6:0] bits
causing the random time variable to be ignored.
Table 144.ꢀRFCR5 register — pseudo-random time variable (address $0035)
Bit
R
7
BOOST
0
6
5
4
3
LFSR[6:0]
0
2
1
0
W
Reset
0
0
0
0
0
0
FXTH87ERM
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Reference manual
Rev. 5.0 — 4 February 2019
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