NXP Semiconductors
FXTH87E
FXTH87E, Family of Tire Pressure Monitor Sensors
Table 145.ꢀRFCR5 field descriptions
Field
Description
BOOST — This bit controls the VCO power consumption in order to decrease the phase noise required by
the Japanese regulation. The BOOST control bit is cleared by the RFMRST signal.
7
0ꢀThe VCO runs at its lower power consumption level (higher phase noise).
1ꢀThe VCO runs at its higher power consumption level (lower phase noise).
BOOST
Pseudo-Random Timer — The LFSR[6:0] bits select the current seed value of the LFSR when enabling
pseudo-random timing intervals when any of the LFSR[6:0] bits are set. The value written to this register is
loaded into the actual LFSR when the SEND bit is set. The time value is equal to a nominal one millisecond
for each count of the resulting LFSR[6:0] bits.
6:0
LFSR[6:0]
A value of $00 placed in the LFSR causes the LFSR to stay at the $00 state on each clocking of the LFSR.
To cause the LFSR to cycle through its pseudo-random number sequence requires that any value other
than $00 be written to the LFSR[6:0] bits.
Note: If RFBT[7:0] and RFFT[5:0] are both set to non-zero, and LFSR[6:0] is set to 0x00,
the system will decrement both RFBT and RFFT simultaneously rather than serially, such
that the effective Interframe Interval will be equal to the larger of RFBT or RFFT settings.
15.15 RFM control register 6 — RFCR6
The RFCR6 register contains eight control bits to set the initial and interframe frame
number timing variable as described in Table 146. A RFMRST signal clears the
RFFT[5:0] bits.
Table 146.ꢀRFCR6 register — frame number time — RFTS[1:0] = 1:0 (address $0036)
Bit
R
7
6
5
4
3
2
1
0
VCO_GAIN[1:0]
RFFT[5:0]
W
Reset
1
0
0
0
0
0
0
0
Table 147.ꢀRFCR6 field descriptions
Field
Description
7:6
VCO Gain Selection — These bits control the VCO gain. The VCO_GAIN[1] bit is set and the VCO_GAIN[0]
bit is cleared by the RFMRST signal. Not normally need to be adjusted by the end user.
VCO_
GAIN[1:0]
Frame Number Timer — The RFFT[5:0] control bits select the interframe timing between multiple frames
of transmission. The time value is equal to a nominal one millisecond for each count of the RFFT[5:0] bits
multiplied by the frame number of the last transmitted frame. The RFFT[5:0] control bits are cleared by the
RFMRST signal.
5:0
RFFT[5:0]
15.16 RFM control register 7 — RFCR7
The RFCR7 register contains four control bits and four status bits for the RFM as
described in Table 148.
Table 148.ꢀRFM transmit control registers (RFCR7) (address $0037)
Bit
7
6
5
4
3
2
1
0
R
RFIF
RFEF
RFVF
0
RFIEN
RFLVDEN
RCTS
0
FXTH87ERM
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Reference manual
Rev. 5.0 — 4 February 2019
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