NXP Semiconductors
FXTH87E
FXTH87E, Family of Tire Pressure Monitor Sensors
15.19 EPR register — EPR (RPAGE = 1)
The EPR register contains eight control bits for the RFM as described in Table 156. The
function of the upper 4 bits depends on the state of the VCD_EN bit.
Table 156.ꢀRFM EPR registers (EPR, RPAGE = 1, VCD_EN = 0) (address $0038)
Bit
7
6
5
4
3
2
1
0
R
W
PLL_LPF_[2:0]
1
PA_SLOPE VCD_EN
RFMRST
0
0
1
0
0
1
0
= Reserved
Table 157.ꢀRFM EPR registers (EPR, RPAGE = 1, VCD_EN = 1) (address $0038)
Bit
7
6
5
4
3
2
1
0
R
W
VCD[3:0]
PA_SLOPE VCD_EN
RFMRST
—
—
—
—
0
0
1
0
= Reserved
Table 158.ꢀEPR field descriptions
Field
Description
7
Reserved bit — Not for user access if the VCD_EN bit is clear.
Reserved
6-4
Low Pass Filter Selection — These read/write bits select the PLL low pass filter. A reset sets these bits to
$03. These bits are only accessible if the VCD_EN bit is clear.
PLL_
LPF_[2:0]
VCO Calibration Count Difference — These read-only bits show the count difference from "ideal" when the
VCO\ calibration machine is finished (see Section 15.21 "VCO calibration machine"). These bits are only
accessible when the VCD_EN bit is set. Writing to these bits when the VCD_EN bit is set has no effect. The
reset state is undefined.
7-4
VCD[3:0]
3-2
Reserved bits — Not for user access.
Reserved
1
PA Output Slope Selection — This read/write bit controls the output slope of the RFM PA output. This bit is
set by the RFMRST signal.
PA_SLOPE
VCD Enable bit — This bit allows access to the VCD[3:0] bits. This bit is cleared by the RFMRST signal.
0ꢀPLL_LPF_[2:0] bits accessed.
0
VCD_EN
1ꢀVCD[3:0] bits accessed.
15.20 RF DATA registers — RFD[31:0]
The RFD registers contain 256 read/write bits for the RFM to use when outputting
data as described in Section 15.2 "RF output buffer data frame". The 256- bit buffer is
FXTH87ERM
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2019. All rights reserved.
Reference manual
Rev. 5.0 — 4 February 2019
154 / 183
NXP [ NXP ]
