NXP Semiconductors
FXTH87E
FXTH87E, Family of Tire Pressure Monitor Sensors
15.18 PLL control registers B - PLLCR[3:2], RPAGE = 0
The PLLCR[3:2] registers contain 16 control bits for the RFM as described in Table 153
and Table 154. These bits are only accessible when the RPAGE bit is cleared.
Table 153.ꢀPLL control registers B (PLLCR[3:2], RPAGE = 0) (address $003A)
Bit
7
6
5
4
3
2
1
0
R
W
BFREQ[12:5]
RFMRST
0
0
0
0
0
0
0
0
Table 154.ꢀPLL control registers B (PLLCR[3:2], RPAGE = 0) (address $003B)
Bit
7
6
5
4
3
2
CF
0
1
MOD
0
0
CKREF
0
R
W
BFREQ[4:0]
0
RFMRST
0
0
0
0
Table 155.ꢀPLLCR[3:2] field descriptions
Field
Description
PLL Divider Ratio B- The BFREQ[12:0] control bits select the PLL divider ratio for a data one in either
the OOK or FSK modes of modulation as described by the following equation:
BFREQ[12:0]
(PLLCR2[7:0],
PLLCR3[7:3])
where:
fCARRIER = RF Carrier frequency in MHz
fXTAL = External crystal frequency in MHz
CF = State of the CF carrier select bit
BFREQ = Decimal value of the BFREQ[12:0] binary weighted bits
The BFREQ[12:0] control bits are cleared by the RFMRST signal. 1 LSB of BFREQ[12:0] = 3.17 kHz.
Carrier Frequency — The CF control bit selects the optimal VCO setup and correct divider for the 500
kHz reference clock to the MCU on DX based on the external crystals required for the desired carrier
frequency. The CF control bit is cleared by the RFMRST signal.
2
CF
0ꢀConfigured for 315 MHz, 12.1154 PLL divider using a 26.000 MHz external crystal.
1ꢀConfigured for 434 MHz, 16.6923 PLL divider using a 26.000 MHz external crystal.
RF Modulation Method — The MOD control bit selects the method of modulating the RF. The MOD
control bit is cleared by the RFMRST signal.
1
0ꢀConfigured for OOK.
1ꢀConfigured for FSK.
MOD
Generated Clock Reference — Generates the DX signal to the TPM1 module for determining the
other clock frequencies:
0
0ꢀDX signal not generated.
CKREF
1ꢀDX 500 kHz signal connected to the TPM1 module.
FXTH87ERM
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Reference manual
Rev. 5.0 — 4 February 2019
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