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A2V07H525-04N 参数 Datasheet PDF下载

A2V07H525-04N图片预览
型号: A2V07H525-04N
PDF下载: 下载PDF文件 查看货源
内容描述: [N--Channel Enhancement--Mode Lateral MOSFET]
分类和应用:
文件页数/大小: 25 页 / 1056 K
品牌: NXP [ NXP ]
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Table 8. Carrier Side Load Pull Performance — Maximum Power Tuning  
V
= 48 Vdc, I  
= 701 mA, Pulsed CW, 10 sec(on), 10% Duty Cycle  
DD  
DQA  
Max Output Power  
P1dB  
(1)  
Z
AM/PM  
()  
f
Z
Z
in  
()  
load  
()  
D
source  
()  
(%)  
58.2  
63.0  
Gain (dB)  
(dBm)  
(W)  
(MHz)  
595  
652  
5.07 – j0.52  
4.10 – j1.84  
5.37 + j0.48  
2.93 + j0.08  
2.99 + j0.54  
20.5  
54.0  
250  
–10  
–9  
3.77 + j2.27  
21.1  
54.2  
262  
Max Output Power  
P3dB  
(2)  
Z
()  
AM/PM  
()  
f
Z
Z
()  
load  
D
source  
()  
in  
(%)  
58.2  
66.7  
Gain (dB)  
18.3  
(dBm)  
54.6  
(W)  
286  
293  
(MHz)  
595  
5.07 – j0.52  
5.12 + j0.52  
2.88 – j0.02  
3.33 + j0.69  
–12  
–11  
652  
4.10 – j1.84  
3.59 + j2.50  
19.3  
54.7  
(1) Load impedance for optimum P1dB power.  
(2) Load impedance for optimum P3dB power.  
Z
Z
Z
= Measured impedance presented to the input of the device at the package reference plane.  
= Impedance as measured from gate contact to ground.  
= Measured impedance presented to the output of the device at the package reference plane.  
source  
in  
load  
Table 9. Carrier Side Load Pull Performance — Maximum Efficiency Tuning  
V
= 48 Vdc, I  
= 701 mA, Pulsed CW, 10 sec(on), 10% Duty Cycle  
DD  
DQA  
Max Drain Efficiency  
P1dB  
(1)  
Z
AM/PM  
()  
f
Z
Z
in  
()  
load  
()  
D
source  
()  
(%)  
68.8  
78.1  
Gain (dB)  
(dBm)  
(W)  
(MHz)  
595  
652  
5.07 – j0.52  
4.10 – j1.84  
4.31 + j0.61  
3.20 + j3.58  
2.12 + j4.47  
23.5  
51.2  
131  
–14  
–13  
2.83 + j2.71  
24.4  
50.1  
102  
Max Drain Efficiency  
P3dB  
(2)  
Z
()  
AM/PM  
()  
f
Z
Z
()  
load  
D
source  
()  
in  
(%)  
67.5  
78.8  
Gain (dB)  
20.8  
(dBm)  
52.9  
(W)  
196  
196  
(MHz)  
595  
5.07 – j0.52  
4.52 + j0.59  
3.30 + j2.55  
3.15 + j3.42  
–16  
–17  
652  
4.10 – j1.84  
3.16 + j2.88  
21.3  
52.9  
(1) Load impedance for optimum P1dB efficiency.  
(2) Load impedance for optimum P3dB efficiency.  
Z
Z
Z
= Measured impedance presented to the input of the device at the package reference plane.  
= Impedance as measured from gate contact to ground.  
= Measured impedance presented to the output of the device at the package reference plane.  
source  
in  
load  
Input Load Pull  
Tuner and Test  
Circuit  
Output Load Pull  
Tuner and Test  
Circuit  
Device  
Under  
Test  
Z
Z
in  
Z
load  
source  
A2V07H525--04NR6  
RF Device Data  
NXP Semiconductors  
7