Nano100(A)
5.10 Timer Controller
5.10.1 Overview
This chip is equipped with four timer modules including TIMER0, TIMER1, TIMER2 and TIMER3
(TIMER0/1 is at APB1 and TIMER2/3 is at APB2), which allow user to easily implement a
counting scheme or timing control for applications. The timer can perform functions like frequency
measurement, event counting, interval measurement, clock generation, delay timing, and so on.
The timer can generate an interrupt signal upon timeout, or provide the current value of count
during operation.
5.10.2 Features
Independent Clock Source for each Timer (TMRx_CLK, x= 0, 1,2,3)
Time out period = (Period of timer clock input) * (8-bit pre-scale counter + 1) * (24-bit
TCMP)
Maximum counting cycle time = (1 / 25 MHz) * (2^8) * (2^24), if TCLK = 25 MHz
Internal 8-bit pre-scale counter
Internal 24-bit up counter is readable through TDR (Timer Data Register)
Supports One-shot, Periodic and Output Toggle Operation mode
Supports external pin capture for interval measurement
Supports external pin capture for timer counter reset
Supports Inter-Timer trigger
Supports Internal trigger event to ADC and PDMA
5.11 Pulse Width Modulation (PWM)
5.11.1 Overview
This chip has two PWM controllers, each controller has 4 independent PWM outputs, CH0~CH3,
or as 2 complementary PWM pairs, (CH0, CH1), (CH2, CH3) with 2 programmable dead-zone
generators.
Each of the two PWM outputs, (CH0, CH1), (CH2, CH3), share the same 8-bit prescaler, clock
divider providing 5 divided frequencies (1, 1/2, 1/4, 1/8, 1/16). Each PWM output has independent
16-bit PWM down-count counter for PWM period control, and 16-bit comparators for PWM duty
control. Each dead-zone generator has two outputs. The first dead-zone generator output is CH0
and CH1, and for the second dead-zone generator, the output is CH2 and CH3. The 2 sets of
PWM controller total provide eight independent PWM interrupt flags which are set by hardware
when the corresponding PWM period down counter reaches 0. PWM interrupt will be asserted
when both PWM interrupt source and its corresponding enable bit are active. Each PWM output
can be configured as one-shot mode to produce only one PWM cycle signal or continuous mode
to output PWM waveform continuously.
When DZEN01 (PWMx_CTL[4]) (x=0,1) is set, CH0 and CH1 perform complementary PWM
paired function; the paired PWM timing, period, duty and dead-time are determined by PWM
channel 0 timer and Dead-zone generator 0. Similarly, When DZEN23 (PWMx_CTL[5]) is set the
complementary PWM pair of (CH2, CH3) is controlled by PWM channel 2.
To prevent PWM driving output pin with unsteady waveform, the 16-bit period down counter and
16-bit comparator are implemented with double buffer. When user writes data to
counter/comparator buffer registers the updated value will be loaded into the 16-bit down counter/
comparator at the time down counter reaching 0. The double buffering feature avoids glitch at
Mar 31, 2015
Page 63 of 95
Revision V1.00
NUVOTON [ NUVOTON ]
