Nano100(A)
5.7 External Bus Interface
5.7.1 Overview
This chip is equipped with an external bus interface (EBI) to access external device. To save the
connections between external device and this chip, EBI support address bus and data bus
multiplex mode. Also, address latch enable (ALE) signal is used to differentiate the address and
data cycle.
5.7.2 Features
External devices with max. 64 Kbytes size (8-bit data width)/128 Kbytes (16-bit data
width) supported
Supports variable external bus base clock (MCLK)
Supports 8-bit or 16-bit data width
Supports variable data access time (tACC), address latch enable time (tALE) and
address hold time (tAHD)
Address bus and data bus multiplex mode supported to save the address pins
Configurable idle cycle supported for different access condition: Write command finish
(W2X), Read-to-Read (R2R), Read-to-Write (R2W)
Supports PDMA and VDMA transfer
5.8 General Purpose I/O Controller
5.8.1 Overview
The NuMicroTM Nano100 series have up to 51 General Purpose I/O pins to be shared with other
function pins depending on the chip configuration. These 51 pins are arranged in 6 ports named
with GPIOA, GPIOB, GPIOC, GPIOD, GPIOE and GPIOF. Each one of the 51 pins is
independent and has the corresponding register bits to control the pin mode function and data.
The I/O type of each of I/O pins can be independently software configured as input, output, and
open-drain mode. Each I/O pin has a very weak individual pull-up resistor which is about 110
K~300 K for VDD from 1.8 V to 3.6 V.
5.8.2 Features
Three I/O modes:
Schmitt trigger Input-only with high impendence
Push-pull output
Open-drain output
I/O pin configured as interrupt source with edge/level setting
Enabling the pin interrupt function will also enable the pin wake-up function
Mar 31, 2015
Page 61 of 95
Revision V1.00
NUVOTON [ NUVOTON ]
