Nano100(A)
5.6 FLASH Memory Controller (FMC)
5.6.1 Overview
This chip is equipped with 32KB/64KB on-chip embedded Flash EPROM for application program
memory (APROM) that can be updated through ISP procedure. In System Programming (ISP)
function enables user to update program memory when chip is soldered on PCB. After chip power
on Cortex-M0 CPU fetches code from APROM or LDROM decided by boot select (CBS) in
Config0. By the way, this chip also provides DATA Flash Region, the data flash is shared with
original program memory and its start address is configurable and defined by user in Config1. The
data flash size is defined by user application request.
5.6.2 Features
AHB interface compatible
Run up to 32 MHz with zero wait state for discontinuous address read access
32KB/64KB application program memory (APROM)
4KB in system programming (ISP) loader program memory (LDROM)
Programmable data flash start address and memory size with 512 bytes page erase
unit
In System Program (ISP)/In Application Program (IAP) to update on chip Flash
EPROM
Mar 31, 2015
Page 60 of 95
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