Nano100(A)
PWM outputs.
When the 16-bit period down counter reaches 0, the interrupt request is generated. If PWM output
is set as continuous mode, when the down counter reaches 0, it is reloaded with CN of
PWMx_DUTYy (y=0~3) Register automatically then start decreases, repeatedly. If the PWM
output is set as one-shot mode, the down counter will stop and generate one interrupt request
when it reaches 0.
The value of PWM counter comparator is used for pulse width modulation. The counter control
logic changes the output level when down-counter value matches the value of compare register.
The alternate feature of the PWM is digital input capture function. If capture function is enabled
the PWM output pin is switched as capture input pin. The capture channel 0 and PWM CH0 share
one timer; and the capture channel 1 and PWM CH1 share one timer, and etc. Therefore user
must setup the PWM timer before enabling capture feature. After capture feature of channel 0 is
enabled, the capture always latches PWM CH0 timer value to Capture Rising Latch Register CRL
(PWMx_CRL0[15:0]) when input channel has a rising transition and latches PWM CH0 timer
value to Capture Falling Latch Register CFL (PWMx_CFL0[15:0]) when input channel has a
falling transition. Capture channel
0 interrupt is programmable by setting CRL_IE0
(PWMx_CAPINTEN[0]) for rising transition or CFL_IE0 (PWMx_CAPINTEN[1]) for falling
transition. Whenever Capture rising event latched for channel 0, the PWM CH0 timer will be
reload at this moment if the corresponding reload enable bit CAPRELOADREN0
(PWMx_CAPCTL[6]) is set.
The maximum captured frequency that PWM can capture is dominated by the capture interrupt
latency. When capture interrupt occurs, software will do at least three steps, they are:
Read PWMx_INTSTS to get interrupt source and Read PWMx_CRLy/PWMx_CFLy(y=0~3) to get
capture value and finally write 1 to clear PWMx_INTSTS. If interrupt latency will take time T0 to
finish, the capture signal mustn’t transient during this interval. In this case, the maximum capture
frequency will be 1/T0.
5.11.2 Features
5.11.2.1 PWM function:
Two PWM controllers, each controller has 4 independent PWM outputs, CH0~CH3, or
as 2 complementary PWM pairs, (CH0, CH1), (CH2, CH3) with 2 programmable
dead-zone generators.
Up to 8 PWM channels or 4 PWM paired channels.
Up to 16 bits PWM counter width.
PWM Interrupt request synchronous with PWM period.
One-shot or Continuous mode.
Four Dead-Zone generators
5.11.2.2 Capture Function:
Timing control logic shared with PWM timer.
8 Capture input channels shared with 8 PWM output channels.
Each channel supports one rising latch register CRL (PWMx_CRL0[15:0]), one falling
latch register CFL (PWMx_CFL0[15:0]) and Capture interrupt flag CAPIF0
(PWMx_CAPINTSTS[0]) .
Eight 16-bit counters for eight capture channels or four 32-bit counter for four capture
channels when cascade is enabled:when CH01CASKEN (PWMx_CAPCTL[13]) is
set ,the original 16-bit counter of channel 1 will combine with channel 0’s 16-bit
counter for channel 0 input capture counting and so does CH23CASKEN
Mar 31, 2015
Page 64 of 95
Revision V1.00
NUVOTON [ NUVOTON ]
