Nano100(A)
5.5 Clock Controller
5.5.1 Overview
The clock controller generates clocks for the whole chip, including system clocks (CPU clock,
HCLKx, and PCLKx) and all peripheral engine clocks. HCLKx means AHB bus clock for
peripherals on AHB bus. PCLKx means APB bus clock for peripherals on APB bus. The clock
controller also implements the power control function with the individually clock ON/OFF control,
clock source selection and a 4-bit clock divider. The chip will not enter power-down mode until
CPU sets the power down enable bit (PD_EN(PWRCTL[6])) and CPU executes the WFI
instruction. In the Power-down mode, clock controller turns off the external high frequency crystal,
internal high frequency oscillator, and system clocks (CPU clock, HCLKx, and PCLKx) to reduce
the power consumption to minimum.
5.5.2 Features
Generates clocks for system clocks and all peripheral engine clocks
Each peripheral engine clock can be turned on/off.
High frequency crystal, internal high frequency oscillator, and system clocks will be
turned off when chip is in Power-down mode.
Mar 31, 2015
Page 59 of 95
Revision V1.00
NUVOTON [ NUVOTON ]
