Nano100(A)
5.9 DMA Controller
5.9.1 Overview
The DMA controller contains a four-channel peripheral direct memory access (PDMA) controller
and a one-channel video direct memory access (VDMA) controller that transfers data to and from
memory or transfer data to and from peripherals.For VDMA channel (DMA CH0), it only supports
block transfer from memory to memory. For PDMA channel (DMA CH1~CH4), there is one-word
buffer as transfer buffer between the Peripherals APB devices and Memory. And for VDMA
channel (DMA CH0), there is a two-word buffer.
User can stop the PDMA or VDMA operation by disable PDMACEN (PDMA_CSRx[0]) or
VDMACEN(VDMA_CSR[0]), respectively.
User can polling TD_IS (PDMA_ISRx[1] or
VDMA_ISRx[1]) or enable TD_IE (PDMA_IERx[1] or VDMA_IERx[1]) and wait interrupt to check
DMA transfer complete. The DMA controller can increase source or destination address, fixed or
wrap around them as well.
5.9.2 Features
Five channels: 1 VDMA channel and 4 PDMA channels. Each channel can support a
unidirectional transfer.
VDMA
Supports Memory-to-memory transfer
Supports block transfer with stride
Supports word/half-word/byte boundary address
Supports address direction: increment and decrement
PDMA
Supports Peripheral-to-memory, memory-to-peripheral, and memory-to-memory
transfer
Supports word boundary address
Supports word alignment transfer length in memory-to-memory mode
Supports word/half-word/byte alignment transfer length in peripheral-to-memory
and memory-to-peripheral mode
Supports word/half-word/byte transfer data width from/to peripheral
Supports address direction: increment, fixed, and wrap around
AMBA AHB Master/Slave interface compatible, for data transfer and register
read/write.
Hardware round robin priority scheme.
Mar 31, 2015
Page 62 of 95
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