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M25PE80-VMN6P 参数 Datasheet PDF下载

M25PE80-VMN6P图片预览
型号: M25PE80-VMN6P
PDF下载: 下载PDF文件 查看货源
内容描述: 8兆位,页擦除串行闪存与字节变性, 75兆赫的SPI总线,标准引脚 [8-Mbit, page-erasable serial flash memory with byte alterability, 75 MHz SPI bus, standard pinout]
分类和应用: 闪存内存集成电路
文件页数/大小: 66 页 / 1387 K
品牌: NUMONYX [ NUMONYX B.V ]
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SPI modes  
M25PE80  
3
SPI modes  
These devices can be driven by a microcontroller with its SPI peripheral running in either of  
the two following modes:  
CPOL=0, CPHA=0  
CPOL=1, CPHA=1  
For these two modes, input data is latched in on the rising edge of serial clock (C), and  
output data is available from the falling edge of serial clock (C).  
The difference between the two modes, as shown in Figure 5, is the clock polarity when the  
bus master is in standby mode and not transferring data:  
C remains at 0 for (CPOL=0, CPHA=0)  
C remains at 1 for (CPOL=1, CPHA=1)  
Figure 4.  
Bus master and memory devices on the SPI bus  
VSS  
VCC  
R
SDO  
SPI interface with  
(CPOL, CPHA) =  
(0, 0) or (1, 1)  
SDI  
SCK  
VCC  
VCC  
VCC  
C
Q
D
C
Q
D
C Q D  
VSS  
VSS  
VSS  
SPI bus master  
SPI memory  
device  
SPI memory  
device  
SPI memory  
device  
R
R
R
CS3 CS2 CS1  
S
S
S
W
Reset  
W
Reset  
Reset  
W
or  
or  
or  
TSL  
TSL  
TSL  
AI13558b  
1. The Top Sector Lock (TSL) signal in the T7Y process, or the Write Protect (W) signal in the T9HX process,  
should be driven, High or Low as appropriate.  
Figure 4 shows an example of three devices connected to an MCU, on an SPI bus. Only one  
device is selected at a time, so only one device drives the serial data output (Q) line at a  
time, the other devices are high impedance. Resistors R (represented in Figure 4) ensure  
that the M25PE80 is not selected if the bus master leaves the S line in the high impedance  
state. As the bus master may enter a state where all inputs/outputs are in high impedance at  
the same time (for example, when the bus master is reset), the clock line (C) must be  
connected to an external pull-down resistor so that, when all inputs/outputs become high  
impedance, the S line is pulled High while the C line is pulled Low (thus ensuring that S and  
C do not become High at the same time, and so, that the t  
requirement is met). The  
SHCH  
typical value of R is 100 k, assuming that the time constant R*C (C = parasitic  
p
p
capacitance of the bus line) is shorter than the time during which the bus master leaves the  
SPI bus in high impedance.  
10/66  
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