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M25PE80-VMN6P 参数 Datasheet PDF下载

M25PE80-VMN6P图片预览
型号: M25PE80-VMN6P
PDF下载: 下载PDF文件 查看货源
内容描述: 8兆位,页擦除串行闪存与字节变性, 75兆赫的SPI总线,标准引脚 [8-Mbit, page-erasable serial flash memory with byte alterability, 75 MHz SPI bus, standard pinout]
分类和应用: 闪存内存集成电路
文件页数/大小: 66 页 / 1387 K
品牌: NUMONYX [ NUMONYX B.V ]
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Signal descriptions  
M25PE80  
2
Signal descriptions  
2.1  
Serial data output (Q)  
This output signal is used to transfer data serially out of the device. Data is shifted out on the  
falling edge of serial clock (C).  
2.2  
2.3  
2.4  
Serial data input (D)  
This input signal is used to transfer data serially into the device. It receives instructions,  
addresses, and the data to be programmed. Values are latched on the rising edge of serial  
clock (C).  
Serial clock (C)  
This input signal provides the timing of the serial interface. Instructions, addresses, or data  
present at serial data input (D) are latched on the rising edge of serial clock (C). Data on  
serial data output (Q) changes after the falling edge of serial clock (C).  
Chip select (S)  
When this input signal is High, the device is deselected and serial data output (Q) is at high  
impedance. Unless an internal read, program, erase or write cycle is in progress, the device  
will be in the standby mode (this is not the deep power-down mode). Driving Chip Select (S)  
Low selects the device, placing it in the active power mode.  
After power-up, a falling edge on Chip Select (S) is required prior to the start of any  
instruction.  
2.5  
Reset (Reset)  
The reset (Reset) input provides a hardware reset for the memory.  
When reset (Reset) is driven High, the memory is in the normal operating mode. When reset  
(Reset) is driven Low, the memory will enter the reset mode. In this mode, the output is high  
impedance.  
Driving reset (Reset) Low while an internal operation is in progress will affect this operation  
(write, program or erase cycle) and data may be lost.  
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