CHAPTER 3 SPECIFICATIONS OF PCI HOST BRIDGE MACRO
Figure 3-10. Main Memory (SDRAM) Read Access (8-Burst)
I_SDCLK
O_HOLDREQ_B
I_HOLDACK_B
O_SD_CS_B
O_SD_RAS_B
O_SD_CAS_B
O_SD_WR_B
O_SD_ADR1 to
O_SD_ADR25
RA
CA0 CA1 CA2 CA3 CA4 CA5 CA6 CA7
I_SD_DATA0 to
I_SD_DATA31
RD0 RD1 RD2 RD3 RD4 RD5 RD6 RD7
O_SD_DQM_B0 to
O_SD_DQM_B3
0000
1111
1111
Remark SDRAM_CTL register WAIT_STATE field = 10, CAS_LATENCY field = 10
49
Application Note U17121EJ1V1AN