CHAPTER 3 SPECIFICATIONS OF PCI HOST BRIDGE MACRO
3.8.2 PCI bus interface timing
The PCI host bridge macro supports the following PCI bus interface timing.
(1) PCI bus master cycle timing
The timing of access from the CPU to the PCI device is shown below.
(a) Configuration read/write cycle, I/O read/write cycle, and memory read/write cycle
(i) Read cycle
Timing type: Configuration register read, internal I/O register read, memory read
Figure 3-11. Read Cycle
PCICLK
AD
FRAME#
IRDY#
DEVSEL#
TRDY#
H
STOP#
(ii) Write cycle
Timing type: Configuration register write, internal I/O register write, memory write
Figure 3-12. Write Cycle
PCICLK
AD
FRAME#
IRDY#
DEVSEL#
TRDY#
H
STOP#
50
Application Note U17121EJ1V1AN
NEC [ NEC ]
