CHAPTER 3 SPECIFICATIONS OF PCI HOST BRIDGE MACRO
(d) Data parity error
Timing type: Single read & write cycle data parity error
Figure 3-15. Data Parity Error
PCICLK
AD
FRAME#
IRDY#
DEVSEL#
TRDY#
STOP#
PAR
H
PERR#
(2) PCI bus slave cycle timing
The timing of access from the PCI device to SDRAM is shown below.
(a) Memory single read cycle
Timing type: Memory single read cycle
Figure 3-16. Single Read Cycle
PCICLK
REQ#
GNT#
AD
FRAME#
IRDY#
DEVSEL#
TRDY#
STOP#
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Application Note U17121EJ1V1AN