CHAPTER 3 SPECIFICATIONS OF PCI HOST BRIDGE MACRO
3.4.6 PCI_INT_CTL register
The PCI_INT_CTL register shows the interrupt sources of the PCI bus error interrupt (O_PCIHOST_INT) and
controls masking and clearing of these interrupts.
This function is used only for debugging and is not used in normal operation.
After reset: 000x0F00H
31
R/W
Offset address: 18H
20 19 18 17 16 15
12 11 10
9
8
7
0
4
0
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit Name
R/W
W
Function
CLR_SERR
CLR_PERR
CLR_MAB
CLR_TAB
Clears the PCI bus system error (SERR# reception) interrupt.
1: Cleared
W
W
W
Clears the PCI bus parity error (PERR# reception) interrupt.
1: Cleared
Clears the PCI bus master abort interrupt.
1: Cleared
Clears the PCI bus target abort interrupt.
1: Cleared
MSK_SERR
R/W Sets the mask status of the PCI bus system error (SERR# reception) interrupt.
0: Not masked
1: Masked
MSK_PERR
MSK_MAB
MSK_TAB
R/W Sets the mask status of the PCI bus parity error (PERR# reception) interrupt.
0: Not masked
1: Masked
R/W Sets the mask status of the PCI bus master abort interrupt.
0: Not masked
1: Masked
R/W Sets the mask status of the PCI bus target abort interrupt.
0: Not masked
1: Masked
SERR
R
R
R
R
Detects the occurrence status of a PCI bus system error (SERR# reception).
1: System error occurred
PERR
Detects the occurrence status of the PCI bus parity error (PERR# reception).
1: Parity error occurred
MABORT
TABORT
Detects the occurrence status of the PCI bus master abort.
1: Master abort occurred
Detects the occurrence status of the PCI bus target abort.
1: Target abort occurred
39
Application Note U17121EJ1V1AN
NEC [ NEC ]
