CHAPTER 3 SPECIFICATIONS OF PCI HOST BRIDGE MACRO
3.3 Pin Functions
The pin functions of each interface are described below.
3.3.1 External bus slave interface pins
Pin Name
I/O
Input
Function
Active
I_SRST_B
System reset input
Low
Low
Low
Low
I_CPU_CS0_B
Input
PCI host bridge register chip select input
PCI I/O area chip select input
PCI memory area chip select input
CPU address input
I_CPU_CS1_B
Input
I_CPU_CS2_B
Input
I_CPU_ADR0 to I_CPU_ADR19
I_CPU_DATA0 to I_CPU_DATA31
O_CPU_DATA0 to O_CPU_DATA31
EN_CPU_DATA
Input
−
−
−
Input
CPU data input
Output
Output
Input
CPU data output
CPU data output enable output
CPU data byte enable input
CPU write data enable input
CPU read data output enable input
CPU data wait output
High
I_CPU_BE_B0 to I_CPU_BE_B3
I_CPU_WE_B
−
Input
Low
Low
Low
Low
I_CPU_OE_B
Input
O_CPU_WAIT_B
Output
Output
Input
O_PCIHOST_INT
PCI host bridge interrupt output
CPU data bus width select input
I_MODE16
Low: 32-bit width
High: 16-bit width
3.3.2 SDRAM bus interface pins
Pin Name
O_HOLDREQ_B
I/O
Output
Input
Function
SDRAM bus hold request output
SDRAM bus hold acknowledge input
SDRAM clock input
Active
Low
Low
−
I_HOLDACK_B
I_SDCLK
Input
O_SD_DATA0 to O_SD_DATA31
I_SD_DATA0 to I_SD_DATA31
EN_SD_DATA0, EN_SD_DATA1
Output
Input
SDRAM data output
−
SDRAM data input
−
Output
SDRAM data enable output
←
Low: Lower 16 bits (O_SD_DATA0 to O_SD_DATA15)
High: Higher 16 bits (O_SD_DATA16 to O_SD_DATA31)
O_SD_DQM_B0 to O_SD_DQM_B3
O_SD_ADR1 to O_SD_ADR25
O_SD_CKE
Output
Output
Output
Output
Output
Output
Output
Output
SDRAM data mask output
Low
−
SDRAM address output
SDRAM clock enable output
SDRAM chip select output
High
Low
Low
Low
Low
High
O_SD_CS_B
O_SD_RAS_B
SDRAM row address strobe output
SDRAM column address strobe output
SDRAM read/write output
O_SD_CAS_B
O_SD_WR_B
EN_SD_CTL
SDRAM control signal output enable output
(Output buffer enable of O_SD_ADR1 to O_SD_ADR25,
O_SD_CKE, O_SD_CS_B, O_SD_RAS_B,
O_SD_CAS_B, and O_SD_WR_B pins)
33
Application Note U17121EJ1V1AN
NEC [ NEC ]
