CHAPTER 2 OVERVIEW OF PCI HOST BRIDGE MACRO
2.2 Features
The features of the PCI host bridge macro are as follows.
• PCI bus master cycle control
PCI configuration register read/write single cycle
PCI I/O register read/write single cycle
PCI memory read/write single cycle
• PCI bus slave cycle control
PCI memory read/write cycle (burst transfer up to 8 doublewords (32 bits × 8 bursts))
• PCI bus arbiter control
Up to 8 masters can be controlled (one of them is occupied by the PCI host bridge macro)
Bus parking master: Limited to PCI host bridge macro/selectable from the last accessed master
• PCI bus error processing
An error interrupt is generated for master abort/target abort/PERR# reception/SERR# reception
The address immediately before an error occurs is retained
• PCI bus address conversion control
PCI I/O address and PCI memory address registers are supported to convert the physical addresses from
the CPU to addresses for the PCI bus
• CPU interface control
External bus interface (MEMC)
Data bus width: 32 bits/16 bits
Cycle control by hardware wait control
• SDRAM control
SDRAM is controlled in response to main memory (SDRAM) access from the PCI device
Data bus width: 16 bits/32 bits are supported
• PCI clock
33 MHz supported
SDRAM control and PCI control clocks are designed to be asynchronous
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Application Note U17121EJ1V1AN
NEC [ NEC ]
