CHAPTER 3 SPECIFICATIONS OF PCI HOST BRIDGE MACRO
3.2 Relationship Between Internal Blocks and Signals
The I/O signals for each block of the PCI host bridge macro are as follows.
Figure 3-2. Blocks and Pin Signals of PCI Host Bridge Macro
External bus interface
I_SRST_B
PCI bus interface
I_PCLK
O_PCIRST_B
I_AD0 to I_AD31
O_AD0 to O_AD31
EN_AD
I_CPU_CS0_B
I_CPU_CS1_B
I_CPU_CS2_B
I_CPU_ADR0 to I_CPU_ADR19
I_CPU_DATA0 to I_CPU_DATA31
O_CPU_DATA0 to O_CPU_DATA31
EN_CPU_DATA
I_CBE0 to I_CBE3
O_CBE0 to O_CBE3
EN_CBE
LM_BRIDGE
I_FRAME_B
O_FRAME_B
EN_FRAME
I_IRDY_B
I_CPU_BE_B0 to I_CPU_BE_B3
I_CPU_WE_B
I_CPU_OE_B
O_CPU_WAIT_B
O_IRDY_B
O_PCIHOST_INT
EN_IRDY
I_MODE16
I_DEVSEL_B
O_DEVSEL_B
EN_DEVSEL
I_TRDY_B
LS_BRIDGE
PH_FLIP_BRIDGE
SDRAM bus interface
O_TRDY_B
EN_TRDY
O_HOLDREQ_B
I_HOLDACK_B
I_STOP_B
I_SDCLK
O_STOP_B
EN_STOP
O_SD_DATA0 to O_SD_DATA31
I_SD_DATA0 to I_SD_DATA31
EN_SD_DATA0, EN_SD_DATA1
O_SD_DQM_B0 to O_SD_DQM_B3
O_SD_ADR1 to O_SD_ADR25
O_SD_CKE
I_PAR
O_PAR
SDRAMC
EN_PAR
I_PERR_B
O_PERR_B
EN_PERR
O_SD_CS_B
O_SD_RAS_B
I_SERR_B
O_SD_CAS_B
I_REQ_B1 to I_REQ_B7
O_GNT_B1 to O_GNT_B7
O_SD_WR_B
EN_SD_CTL
32
Application Note U17121EJ1V1AN
NEC [ NEC ]
