µPD703100A-33, 703100A-40, 703101A-33, 703102A-33
(5) Page ROM access timing (1/2)
Parameter
Symbol
<24>
Condition
MIN.
10
MAX.
Unit
ns
WAIT setup time (to CLKOUT ↓)
WAIT hold time (from CLKOUT ↓)
tSWK
tHKW
tSKID
<25>
<26>
2
ns
Data input setup time
10
ns
(to CLKOUT ↑)
Data input hold time
<27>
<30>
tHKID
2
ns
ns
(from CLKOUT ↑)
Off-page data input setup time (to
address)
tSAID
(1.5 + wD + w) T – 20
(1 + wD + w) T – 24
Off-page data input setup time (to RD)
Off-page RD low-level width
RD high-level width
<31>
<32>
<33>
<36>
<37>
<53>
tSRDID
tWRDL
ns
ns
ns
ns
ns
ns
(1 + wD + w) T – 10
0.5T – 10
tWRDH
tHRDID
tDRDOD
tWORDL
Data input hold time (from RD)
Data output delay time from RD ↑
On-page RD low-level width
0
(0.5 + i) T – 10
(1.5 + wPR + w)
T – 10
On-page data input setup time
(to address)
<54>
<55>
tSOAID
(1.5 + wPR + w) T – 20
(1.5 + wPR + w) T – 24
ns
ns
On-page data input setup time (to RD)
tSORDID
Remarks 1. T = tCYK
2. w: the number of waits due to WAIT.
3. wD: the number of waits due to the DWC1 and DWC2 registers.
4. wPR: the number of waits due to the PRC register.
5. i: the number of idle states that are inserted when a write cycle follows a read cycle.
6. Maintain at least one of the data input hold times tHKID and tHRDID.
90
Preliminary Data Sheet U14168EJ2V0DS00
NEC [ NEC ]
