µPD703100A-33, 703100A-40, 703101A-33, 703102A-33
(e) DMA flyby transfer timing (external I/O → SRAM transfer) (1/2)
Parameter
Symbol
<24> tSWK
tHKW
Condition
MIN.
10
MAX.
Unit
ns
WAIT setup time (to CLKOUT ↓)
WAIT hold time (from CLKOUT ↓)
IORD low-level width
<25>
<32>
2
ns
tWRDL
(1 + wD + wF + w)
T – 10
ns
IORD high-level width
<33>
<34>
<35>
<37>
<38>
<39>
<40>
<41>
<42>
<43>
tWRDH
tDARD
tDRDA
tDRDOD
tSAW
T – 10
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
IORD ↓ delay time from address, CSn
Address delay time from IORD ↑
Data output delay time from IORD ↑
WAIT setup time (to address)
0.5T – 5
(0.5 + i) T – 5
(0.5 + i) T – 10
Note
Note
Note
T – 20
T – 20
WAIT setup time (to BCYST ↓)
WAIT hold time (from BCYST ↑)
UWR, LWR ↓ delay time from address
Address setup time (to UWR, LWR ↑)
tSBSW
tHBSW
tDAWR
tSAWR
tDWRA
0
0.5T – 5
(1.5 + wD + w) T – 10
0.5T – 5
Address delay time from UWR, LWR,
IOWR ↑
UWR, LWR high-level width
<44>
<45>
<48>
tWWRH
tWWRL
tDWRRD
T – 10
(1 + wD + w) T – 10
0
ns
ns
ns
ns
ns
ns
UWR, LWR low-level width
IORD ↑ delay time from UWR, LWR↑
wF = 0
wF = 1
T – 10
IORD ↓ delay time from DMAAKm ↓
DMAAKm ↑ delay time from IORD ↑
<51>
<52>
tDDARD
tDRDDA
0.5T – 10
0.5T – 10
Note For first WAIT sampling when the number of waits due to the DWC1 and DWC2 registers is zero.
Remarks 1. T = tCYK
2. w: the number of waits due to WAIT.
3. wD: the number of waits due to the DWC1 and DWC2 registers.
4. wF: the number of waits that are inserted for a source-side access during a DMA flyby transfer.
5. i: the number of idle states that are inserted when a write cycle follows a read cycle.
6. n = 0 to 7, m = 0 to 3
88
Preliminary Data Sheet U14168EJ2V0DS00
NEC [ NEC ]
