µPD703100A-33, 703100A-40, 703101A-33, 703102A-33
(6) DRAM access timing
(a) Read timing (high-speed page DRAM access, normal access: off-page) (1/3)
Parameter
Symbol
<24>
Condition
MIN.
MAX.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
WAIT setup time (to CLKOUT ↓)
WAIT hold time (from CLKOUT ↓)
Data input setup time (to CLKOUT ↑)
Data input hold time (from CLKOUT ↑)
Data output delay time from OE ↑
Row address setup time
tSWK
tHKW
tSKID
tHKID
tDRDOD
tASR
10
<25>
<26>
<27>
<37>
<56>
<57>
<58>
<59>
<60>
2
10
2
(0.5 + i) T – 10
(0.5 + wRP) T – 10
(0.5 + wRH) T – 10
0.5T – 10
Row address hold time
tRAH
tASC
tCAH
tRC
Column address setup time
Column address hold time
(1.5 + wDA + w) T – 10
Read/write cycle time
(3 + wRP + wRH + wDA + w)
T – 10
RAS precharge time
RAS pulse time
<61>
<62>
tRP
(0.5 + wRP) T – 5
ns
ns
tRAS
(2.5 + wRH + wDA + w)
T – 10
RAS hold time
<63>
<64>
<65>
<66>
<67>
tRSH
tRAL
tCAS
tCRP
tCSH
(1.5 + wDA + w) T – 10
(2 + wDA + w) T – 10
(1 + wDA + w) T – 10
(1 + wRP) T – 10
ns
ns
ns
ns
ns
Column address read time for RAS
CAS pulse width
CAS-RAS precharge time
CAS hold time
(2 + wRH + wDA + w)
T – 10
WE setup time
<68>
<69>
<70>
<71>
<72>
tRCS
tRRH
tRCH
tCPN
tOEA
(2 + wRP + wRH) T – 10
0.5T – 10
ns
ns
ns
ns
ns
WE hold time (from RAS ↑)
WE hold time (from CAS ↑)
CAS precharge time
T – 10
(2 + wRP + wRH) T – 5
Output enable access time
(2 + wRP + wRH + wDA + w)
T – 20
RAS access time
<73>
tRAC
(2 + wRH + wDA + w)
T – 20
ns
Access time from column address
CAS access time
<74>
<75>
tAA
(1.5 + wDA + w) T – 20
(1 + wDA + w) T – 20
ns
ns
tCAC
Remarks 1. T = tCYK
2. w: the number of waits due to WAIT.
3. wRP: the number of waits due to the RPCxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to
13).
4. wRH: the number of waits due to the RHCxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to
13).
5. wDA: the number of waits due to the DACxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to
13).
6. i: the number of idle states that are inserted when a write cycle follows a read cycle.
92
Preliminary Data Sheet U14168EJ2V0DS00
NEC [ NEC ]
