µPD703100A-33, 703100A-40, 703101A-33, 703102A-33
(a) Read timing (high-speed page DRAM access, normal access: off-page) (3/3)
TRPW
T1
TRHW
T2
TDAW
TW
T3
CLKOUT (Output)
A0 to A23 (Output)
RASn (Output)
<58>
<56>
<61>
<57>
<59>
Row address
Column address
<63>
<64>
<76>
<62>
<60>
<67>
<77>
<65>
<66>
UCAS (Output)
LCAS (Output)
<69>
<70>
<71>
<68>
<73>
<75>
WE (Output)
OE (Output)
<79>
<74>
<27>
<72>
<37>
<78>
<26>
D0 to D15 (I/O)
<24>
<25>
<24>
<25>
WAIT (Input)
Remarks 1. This is the timing for the following case (n = 0 to 3, xx = 00 to 03, 10 to 13).
Number of waits due to the RPCxx bit of the DRCn register (TRPW): 1
Number of waits due to the RHCxx bit of the DRCn register (TRHW): 1
Number of waits due to the DACxx bit of the DRCn register (TDAW): 1
2. The broken lines indicate high impedance.
3. n = 0 to 7
94
Preliminary Data Sheet U14168EJ2V0DS00
NEC [ NEC ]
