MU9C4480A/L
SWITCHING CHARACTERISTICS (see Note 3)
Cycle Time
-70
-90
-12
Available
·
4480A
4480L
·
·
Consult factory for availability
·
·
·
·
··
No
1
Symbol
Parameter (all times in nanoseconds)
Min Max Min Max Min Max Notes
t
ELEL
Chip Enable Compare Cycle Time
Chip Enable LOW Pulse Width
70
15
35
55
15
0
90
25
50
75
15
0
120
35
75
100
20
0
t
Short Cycle:
Medium Cycle:
Long Cycle:
2
ELEH
4
4
4
t
3
4
5
6
7
EHEL
Chip Enable HIGH Pulse Width
t
t
t
CVEL
ELCX
Control Input to Chip Enable LOW Set-up Time
Control Input from Chip Enable LOW Hold Time
Chip Enable LOW to Outputs Active
5
5
10
3
10
3
15
3
ELQX
6
t
ELQV
Chip Enable LOW to Outputs Valid
30
52
10
50
75
15
70
85
20
4,6
4,6
7
t
8
EHQZ
Chip Enable HIGH to Outputs High-Z
Data to Chip Enable LOW Set-up Time
Data from Chip Enable LOW Hold Time
Full In Valid to Chip Enable LOW Set-up Time
Full In Valid to Full Flag Valid
3
0
3
0
3
0
t
9
DVEL
t
10
11
12
13
14
15
16
17
18
19
ELDX
10
0
10
0
15
0
t
FIVEL
t
FIVFFV
5
7
8
t
ELFFV
Chip Enable LOW to Full Flag Valid
50
75
90
t
MIVEL
Match in Valid to Chip Enable LOW Set-up Time
Chip Enable HIGH to /MF, /MA, /MM Invalid
0
0
0
0
0
0
t
EHMFX
t
MIVMFV Match In Valid to /MF, /MA, /MM Valid
5
7
8
t
EHMFV
Chip Enable HIGH to /MF Valid
16
18
25
25
30
30
t
EHMXV Chip Enable HIGH to /MA and /MM Valid
t
RLRH
Reset LOW Pulse Width
100
100
100
8
Notes:
1. -1.0V for a duration of 10 ns measured at the 50% amplitude points for Input-only lines (Figure 8).
2. Common I/O lines are clamped, so that signal transients cannot fall below -0.5V.
3. Over ambient operating temperature and Vcc(min) to Vcc(max).
4. See Table 7 on page 20.
5. Control signals are /W, /CM, and /EC.
6. With load specified in Figure 7, Test Load A.
7. With load specified in Figure 7, Test Load B.
8. /E must be HIGH during this period to ensure accurate default values in the configuration registers.
9. With output and I/O pins unloaded.
10. TEST1 and TEST2 may not be implemented on all versions of these products.
Rev. 3a
24
MUSIC [ MUSIC SEMICONDUCTORS ]
