NB671, 24V, HIGH CURRENT SYNCHRONOUS STEP-DOWN CONVERTER
APPLICATION INFORMATION
Setting the Output Voltage---without external
compensation
through resistor R4 and capacitor C4.The output
voltage is influenced by ramp voltage VRAMP
besides R divider as shown in Figure 11. The
For applications that electrolytic capacitor or POS
capacitor with a controlled output of ESR is set
VRAMP can be calculated as shown in equation 7.
R2 should be chosen reasonably, a small R2 will
lead to considerable quiescent current loss while
too large R2 makes the FB noise sensitive. It is
recommended to choose a value within 5kꢀ-
100kꢀ for R2.Typically, set the current through
R2 between 5-30uA will make a good balance
between system stability and also the no load
loss. And the value of R1 then is determined as
follow:
as
output
capacitors,
or
the
internal
compensation is enough for a stable operation
when ceramic capacitors is used, then the
external compensation is not need.. The output
voltage is set by feedback resistors R1 and R2.
As Figure 10 shows.
R2
(14)
R1=
V
R2
FB(AVG)
-
(VOUT -VFB(AVG) ) R4 +R9
The VFB(AVG) is the average value on the FB,
VFB(AVG) varies with the Vin, Vo, and load
condition, etc., its value on the skip mode would
be lower than that of the PWM mode, which
means the load regulation is strictly related to the
Figure10—Simplified Circuit of POS Capacitor
First, choose a value for R2. R2 should be
chosen reasonably, a small R2 will lead to
considerable quiescent current loss while too
large R2 makes the FB noise sensitive. It is
recommended to choose a value within 5kꢀ-
100kꢀ for R2,.Typically, set the current through
R2 between 5-30uA will make a good balance
between system stability and also the no load
loss. Then R1 is determined as follow with the
output ripple considered:
V
V
FB(AVG). Also the line regulation is related to the
FB(AVG). If one wants to gets a better load or line
regulation, a lower Vramp is suggested, as long
as the criterion shown in equation 8 can be met.
For PWM operation, VFB(AVG) value can be
deduced from the equation below.
1
R1 //R2
(15)
V
= VREF + VRAMP
×
FB(AVG)
2
R1 //R2 +R9
1
VOUT
−
ΔVOUT − VREF
Usually, R9 is set to 0ꢀ, and it can also be set
following equation 14 for a better noise immunity.
It should also set to be 5 times smaller than
R1//R2 to minimize its influence on Vramp.
2
(13)
R1 =
⋅R2
VREF
ΔVOUT is the output ripple.
Setting the Output Voltage---with external
compensation
1
(16)
R9 =
2π×C4 ×2F
SW
Using equation 13 to calculate the R1 can be
complicated. To simplify the calculation, a DC-
blocking capacitor Cdc can be added to filter the
DC influence from R4 and R9. Figure 12 shows
a
simplified circuit with external ramp
compensation and a DC-blocking capacitor. With
this capacitor, R1 can easily be obtained by
Figure11—Simplified Circuit of Ceramic
Capacitor
If the system is not stable enough when low ESR
ceramic capacitor is used in the output, an
external voltage ramp should be added to FB
NB671 Rev. 1.0
1/14/2013
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