NB671, 24V, HIGH CURRENT SYNCHRONOUS STEP-DOWN CONVERTER
using the simplified equation for PWM mode
operation:
IOUT
2
ICIN
=
(19)
1
(VOUT − VREF − VRAMP
)
For simplification, choose the input capacitor with
an RMS current rating greater than half of the
maximum load current.
2
(17)
R1 =
R2
1
VREF + VRAMP
2
Cdc is suggested to be at least 10 times larger
than C4 for better DC blocking performance, and
should also not larger than 0.47uF considering
start up performance. In case one wants to use
larger Cdc for a better FB noise immunity,
combined with reduced R1 and R2 to limit the
Cdc in a reasonable value without affecting the
system start up. Be noted that even when the
Cdc is applied, the load and line regulation are
still Vramp related.
The input capacitance value determines the input
voltage ripple of the converter. If there is an input
voltage ripple requirement in the system, choose
the input capacitor that meets the specification.
The input voltage ripple can be estimated as
follows:
IOUT
SW ×CIN
VOUT
VOUT
ΔV =
×
×(1−
)
(20)
IN
F
V
V
IN
IN
Under worst-case conditions where VIN = 2VOUT
:
IOUT
4 FSW ×CIN
1
ΔV =
×
(21)
IN
Output Capacitor
The output capacitor is required to maintain the
DC output voltage. Ceramic or POSCAP
capacitors are recommended. The output voltage
ripple can be estimated as:
Figure12—Simplified Circuit of Ceramic
Capacitor with DC blocking capacitor
VOUT
V
1
(22)
)
ΔVOUT
=
×(1− OUT )×(RESR
+
Input Capacitor
FSW ×L
V
8×FSW ×COUT
IN
The input current to the step-down converter is
discontinuous and therefore requires a capacitor
to supply the AC current to the step-down
converter while maintaining the DC input voltage.
Ceramic capacitors are recommended for best
performance and should be placed as close to
the VIN pin as possible. Capacitors with X5R and
X7R ceramic dielectrics are recommended
because they are fairly stable with temperature
fluctuations.
In the case of ceramic capacitors, the impedance
at the switching frequency is dominated by the
capacitance. The output voltage ripple is mainly
caused by the capacitance. For simplification, the
output voltage ripple can be estimated as:
VOUT
VOUT
(23)
ΔVOUT
=
×(1−
)
8×F 2 ×L×COUT
V
SW
IN
The output voltage ripple caused by ESR is very
small. Therefore, an external ramp is needed to
stabilize the system. The external ramp can be
generated through resistor R4 and capacitor C4.
The capacitors must also have a ripple current
rating greater than the maximum input ripple
current of the converter. The input ripple current
can be estimated as follows:
In the case of POSCAP capacitors, the ESR
dominates the impedance at the switching
frequency. The ramp voltage generated from the
ESR is high enough to stabilize the system.
Therefore, an external ramp is not needed. A
minimum ESR value around 12mꢀ is required to
ensure stable operation of the converter. For
VOUT
VOUT
(18)
ICIN = IOUT
×
×(1−
)
V
V
IN
IN
The worst-case condition occurs at VIN = 2VOUT
,
where:
NB671 Rev. 1.0
1/14/2013
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16
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