SPI Master AC Electrical Specifications
Table 11-22. SPI Master Timing
All Frequencies
Num
Characteristic
Unit
Min
Max
160 MASTER cycle time
4
2
1024
512
—
t
t
cyc
161 MASTER clock (SCK) high or low time
162 MASTER data setup time (inputs)
163 Master data hold time (inputs)
164 Master data valid (after SCK edge)
165 Master data hold time (outputs)
166 Rise time output
cyc
50
0
ns
ns
ns
ns
ns
ns
—
—
0
20
—
—
—
15
167 Fall time output
15
SPICLK
(CI=0)
(Output)
161
163
167
166
167
161
160
SPICLK
(CI=1)
(Output)
162
166
Data
165
SPIMISO
(Input)
msb
167
lsb
msb
164
166
SPIMOSI
(Output)
msb
Data
lsb
msb
Figure 11-63. SPI Master (CP = 0) Timing Diagram
MOTOROLA
MPC860 Family Hardware Specifications
61