Ethernet Electrical Specifications
TCLK1
128
128
129
131
121
TxD1
(Output)
132
133
134
TENA(RTS1)
(Input)
RENA(CD1)
(Input)
(NOTE 2)
NOTES:
1. Transmit clock invert (TCI) bit in GSMR is set.
2. If RENA is deasserted before TENA, or RENA is not asserted at all during transmit, then the
CSL bit is set in the buffer descriptor at the end of the frame transmission.
Figure 11-59. Ethernet Transmit Timing Diagram
RCLK1
RxD1
(Input)
0
1
1
BIT1
125
BIT2
136
Start Frame
RSTRT
(Output)
Figure 11-60. CAM Interface Receive Start Timing Diagram
REJECT
137
Figure 11-61. CAM Interface REJECT Timing Diagram
MOTOROLA
MPC860 Family Hardware Specifications
59
MOTOROLA [ MOTOROLA ]
