UTOPIA AC Electrical Specifications
1
SCL frequency is given by SCL = BRGCLK_frequency / ((BRG register + 3) × pre_scaler × 2).
The ratio SYNCCLK/(BRGCLK / pre_scaler) must be greater or equal to 4/1.
Figure 11-67 shows the I2C bus timing.
SDA
202
203
204
208
205
207
SCL
206
209
210
211
2
Figure 11-67. I C Bus Timing Diagram
Part XII UTOPIA AC Electrical Specifications
Table 12-26 shows the AC electrical specifications for the UTOPIA interface.
Table 12-26. UTOPIA AC Electrical Specifications
Num
Signal Characteristic
Direction
Min
Max
Unit
U1
UtpClk rise/fall time (Internal clock option)
Output
—
50
—
—
40
—
2
3.5
50
50
3.5
60
50
16
—
ns
%
Duty cycle
Frequency
MHz
ns
U1a UtpClk rise/fall time (external clock option)
Input
Duty cycle
Frequency
%
MHz
ns
U2
U3
U4
U5
RxEnb and TxEnb active delay
Output
Input
UTPB, SOC, Rxclav and Txclav setup time
UTPB, SOC, Rxclav and Txclav hold time
8
ns
Input
1
—
ns
UTPB, SOC active delay (and PHREQ and PHSEL active delay
in MPHY mode)
Output
2
16
ns
Figure 12-68 shows signal timings during UTOPIA receive operations.
MOTOROLA
MPC860 Family Hardware Specifications
65
MOTOROLA [ MOTOROLA ]
