Ethernet Electrical Specifications
Table 11-20. Ethernet Timing (continued)
All Frequencies
Num
Characteristic
Unit
Min
Max
134 TENA inactive delay (from TCLK1 rising edge)
135 RSTRT active delay (from TCLK1 falling edge)
136 RSTRT inactive delay (from TCLK1 falling edge)
137 REJECT width low
10
10
10
1
50
50
50
—
20
20
ns
ns
ns
CLK
ns
2
138 CLKO1 low to SDACK asserted
—
—
2
139 CLKO1 low to SDACK negated
ns
1
2
The ratios SYNCCLK/RCLK1 and SYNCCLK/TCLK1 must be greater or equal to 2/1.
SDACK is asserted whenever the SDMA writes the incoming frame DA into memory.
CLSN(CTS1)
(Input)
120
Figure 11-57. Ethernet Collision Timing Diagram
RCLK1
121
121
124
123
Last Bit
RxD1
(Input)
125
126
127
RENA(CD1)
(Input)
Figure 11-58. Ethernet Receive Timing Diagram
58
MPC860 Family Hardware Specifications
MOTOROLA
MOTOROLA [ MOTOROLA ]
