SPI Slave AC Electrical Specifications
SPICLK
(CI=0)
(Output)
161
167
166
167
161
160
SPICLK
(CI=1)
(Output)
163
162
166
SPIMISO
(Input)
msb
167
Data
165
lsb
msb
164
166
SPIMOSI
(Output)
msb
Data
lsb
msb
Figure 11-64. SPI Master (CP = 1) Timing Diagram
11.10SPI Slave AC Electrical Specifications
Table 11-23 provides the SPI slave timings as shown in Figure 11-65 and Figure 11-66.
Table 11-23. SPI Slave Timing
All Frequencies
Num
Characteristic
Unit
Min
Max
170 Slave cycle time
2
—
—
—
—
—
—
—
50
t
cyc
171 Slave enable lead time
172 Slave enable lag time
15
15
1
ns
ns
173 Slave clock (SPICLK) high or low time
174 Slave sequential transfer delay (does not require deselect)
175 Slave data setup time (inputs)
t
cyc
cyc
1
t
20
20
—
ns
ns
ns
176 Slave data hold time (inputs)
177 Slave access time
62
MPC860 Family Hardware Specifications
MOTOROLA
MOTOROLA [ MOTOROLA ]
