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SPAKDSP303VF100 参数 Datasheet PDF下载

SPAKDSP303VF100图片预览
型号: SPAKDSP303VF100
PDF下载: 下载PDF文件 查看货源
内容描述: [Digital Signal Processor, 24-Ext Bit, 100MHz, CMOS, PBGA196, 15 X 15 MM, 1 MM PITCH, MOLD ARRAY PROCESS, BGA-196]
分类和应用: 时钟外围集成电路
文件页数/大小: 112 页 / 1117 K
品牌: MOTOROLA [ MOTOROLA ]
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Power Consumption Benchmark  
;
;
;
;
;
EQUATES for DSP56303 I/O registers and ports  
Last update: June 11 1995  
;**************************************************************************  
page  
opt  
132,55,0,0,0  
mex  
ioequ  
ident  
1,0  
;------------------------------------------------------------------------  
;
;
;
EQUATES for I/O Port Programming  
;------------------------------------------------------------------------  
;
Register Addresses  
M_HDR EQU $FFFFC9  
M_HDDR EQU $FFFFC8  
M_PCRC EQU $FFFFBF  
M_PRRC EQU $FFFFBE  
M_PDRC EQU $FFFFBD  
M_PCRD EQU $FFFFAF  
M_PRRD EQU $FFFFAE  
M_PDRD EQU $FFFFAD  
M_PCRE EQU $FFFF9F  
M_PRRE EQU $FFFF9E  
M_PDRE EQU $FFFF9D  
M_OGDB EQU $FFFFFC  
; Host port GPIO data Register  
; Host port GPIO direction Register  
; Port C Control Register  
; Port C Direction Register  
; Port C GPIO Data Register  
; Port D Control register  
; Port D Direction Data Register  
; Port D GPIO Data Register  
; Port E Control register  
; Port E Direction Register  
; Port E Data Register  
; OnCE GDB Register  
;------------------------------------------------------------------------  
;
;
;
EQUATES for Host Interface  
;------------------------------------------------------------------------  
;
Register Addresses  
M_HCR EQU $FFFFC2  
M_HSR EQU $FFFFC3  
M_HPCR EQU $FFFFC4  
M_HBAR EQU $FFFFC5  
M_HRX EQU $FFFFC6  
M_HTX EQU $FFFFC7  
; Host Control Register  
; Host Status Register  
; Host Polarity Control Register  
; Host Base Address Register  
; Host Receive Register  
; Host Transmit Register  
;
HCR bits definition  
M_HRIE EQU $0  
M_HTIE EQU $1  
M_HCIE EQU $2  
M_HF2 EQU $3  
M_HF3 EQU $4  
; Host Receive interrupts Enable  
; Host Transmit Interrupt Enable  
; Host Command Interrupt Enable  
; Host Flag 2  
; Host Flag 3  
;
HSR bits definition  
M_HRDF EQU $0  
M_HTDE EQU $1  
M_HCP EQU $2  
M_HF0 EQU $3  
M_HF1 EQU $4  
; Host Receive Data Full  
; Host Receive Data Empty  
; Host Command Pending  
; Host Flag 0  
; Host Flag 1  
;
HPCR bits definition  
M_HGEN EQU $0  
M_HA8EN EQU $1  
M_HA9EN EQU $2  
M_HCSEN EQU $3  
M_HREN EQU $4  
M_HAEN EQU $5  
M_HEN EQU $6  
M_HOD EQU $8  
M_HDSP EQU $9  
M_HASP EQU $A  
M_HMUX EQU $B  
M_HD_HS EQU $C  
M_HCSP EQU $D  
M_HRP EQU $E  
M_HAP EQU $F  
; Host Port GPIO Enable  
; Host Address 8 Enable  
; Host Address 9 Enable  
; Host Chip Select Enable  
; Host Request Enable  
; Host Acknowledge Enable  
; Host Enable  
; Host Request Open Drain mode  
; Host Data Strobe Polarity  
; Host Address Strobe Polarity  
; Host Multiplexed bus select  
; Host Double/Single Strobe select  
; Host Chip Select Polarity  
; Host Request Polarity  
; Host Acknowledge Polarity  
A-4  
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