Power Consumption Benchmark
;
Register Addresses Of SSI1
M_TX10 EQU $FFFFAC
M_TX11 EQU $FFFFAB
M_TX12 EQU $FFFFAA
M_TSR1 EQU $FFFFA9
M_RX1 EQU $FFFFA8
M_SSISR1 EQU $FFFFA7
M_CRB1 EQU $FFFFA6
M_CRA1 EQU $FFFFA5
M_TSMA1 EQU $FFFFA4
M_TSMB1 EQU $FFFFA3
M_RSMA1 EQU $FFFFA2
M_RSMB1 EQU $FFFFA1
; SSI1 Transmit Data Register 0
; SSI1 Transmit Data Register 1
; SSI1 Transmit Data Register 2
; SSI1 Time Slot Register
; SSI1 Receive Data Register
; SSI1 Status Register
; SSI1 Control Register B
; SSI1 Control Register A
; SSI1 Transmit Slot Mask Register A
; SSI1 Transmit Slot Mask Register B
; SSI1 Receive Slot Mask Register A
; SSI1 Receive Slot Mask Register B
;
SSI Control Register A Bit Flags
M_PM EQU $FF
; Prescale Modulus Select Mask (PM0-PM7)
; Prescaler Range
M_PSR EQU 11
M_DC EQU $1F000
M_ALC EQU 18
M_WL EQU $380000
M_SSC1 EQU 22
; Frame Rate Divider Control Mask (DC0-DC7)
; Alignment Control (ALC)
; Word Length Control Mask (WL0-WL7)
; Select SC1 as TR #0 drive enable (SSC1)
;
SSI Control Register B Bit Flags
M_OF EQU $3
; Serial Output Flag Mask
; Serial Output Flag 0
; Serial Output Flag 1
M_OF0 EQU 0
M_OF1 EQU 1
M_SCD EQU $1C
M_SCD0 EQU 2
M_SCD1 EQU 3
M_SCD2 EQU 4
M_SCKD EQU 5
M_SHFD EQU 6
M_FSL EQU $180
M_FSL0 EQU 7
M_FSL1 EQU 8
M_FSR EQU 9
M_FSP EQU 10
M_CKP EQU 11
M_SYN EQU 12
M_MOD EQU 13
M_SSTE EQU $1C000
M_SSTE2 EQU 14
M_SSTE1 EQU 15
M_SSTE0 EQU 16
M_SSRE EQU 17
M_SSTIE EQU 18
M_SSRIE EQU 19
M_STLIE EQU 20
M_SRLIE EQU 21
M_STEIE EQU 22
M_SREIE EQU 23
; Serial Control Direction Mask
; Serial Control 0 Direction
; Serial Control 1 Direction
; Serial Control 2 Direction
; Clock Source Direction
; Shift Direction
; Frame Sync Length Mask (FSL0-FSL1)
; Frame Sync Length 0
; Frame Sync Length 1
; Frame Sync Relative Timing
; Frame Sync Polarity
; Clock Polarity
; Sync/Async Control
; SSI Mode Select
; SSI Transmit enable Mask
; SSI Transmit #2 Enable
; SSI Transmit #1 Enable
; SSI Transmit #0 Enable
; SSI Receive Enable
; SSI Transmit Interrupt Enable
; SSI Receive Interrupt Enable
; SSI Transmit Last Slot Interrupt Enable
; SSI Receive Last Slot Interrupt Enable
; SSI Transmit Error Interrupt Enable
; SI Receive Error Interrupt Enable
;
SSI Status Register Bit Flags
M_IF EQU $3
M_IF0 EQU 0
M_IF1 EQU 1
M_TFS EQU 2
M_RFS EQU 3
M_TUE EQU 4
M_ROE EQU 5
M_TDE EQU 6
M_RDF EQU 7
; Serial Input Flag Mask
; Serial Input Flag 0
; Serial Input Flag 1
; Transmit Frame Sync Flag
; Receive Frame Sync Flag
; Transmitter Underrun Error FLag
; Receiver Overrun Error Flag
; Transmit Data Register Empty
; Receive Data Register Full
;
SSI Transmit Slot Mask Register A
M_SSTSA EQU $FFFF
; SSI Transmit Slot Bits Mask A (TS0-TS15)
; SSI Transmit Slot Bits Mask B (TS16-TS31)
; SSI Receive Slot Bits Mask A (RS0-RS15)
; SSI Receive Slot Bits Mask B (RS16-RS31)
;
SSI Transmit Slot Mask Register B
M_SSTSB EQU $FFFF
;
SSI Receive Slot Mask Register A
M_SSRSA EQU $FFFF
;
SSI Receive Slot Mask Register B
M_SSRSB EQU $FFFF
A-6
MOTOROLA [ MOTOROLA ]
