5.10.2.4 BDM Commands
Commands consist of one 16-bit operation word and can include one or more 16-bit
extension words. Each incoming word is read as it is assembled by the serial interface.
The microcode routine corresponding to a command is executed as soon as the com-
mand is complete. Result operands are loaded into the output shift register to be shift-
ed out as the next command is read. This process is repeated for each command until
the CPU returns to normal operating mode. Table 5-5 is a summary of background
mode commands.
Table 5-5 Background Mode Command Summary
Command
Read D/A Register
Mnemonic
Description
RDREG/RAREG Read the selected address or data register and
return the results via the serial interface.
Write D/A Register
WDREG/WAREG The data operand is written to the specified ad-
dress or data register.
Read System Register
RSREG
The specified system control register is read. All
registers that can be read in supervisor mode can
be read in background mode.
Write System Register
Read Memory Location
WSREG
READ
The operand data is written into the specified sys-
tem control register.
5
Read the sized data at the memory location spec-
ified by the long-word address. The source func-
tion code register (SFC) determines the address
space accessed.
Write Memory Location
Dump Memory Block
WRITE
DUMP
Write the operand data to the memory location
specified by the long-word address. The destina-
tion function code (DFC) register determines the
address space accessed.
Used in conjunction with the READ command to
dump large blocks of memory. An initial READ is
executed to set up the starting address of the
block and retrieve the first result. Subsequent op-
erands are retrieved with the DUMP command.
Fill Memory Block
FILL
Used in conjunction with the WRITE command to
fill large blocks of memory. An initial WRITE is ex-
ecuted to set up the starting address of the block
and supply the first operand. Subsequent oper-
ands are written with the FILL command.
Resume Execution
Patch User Code
GO
The pipe is flushed and re-filled before resuming
instruction execution at the current PC.
CALL
Current program counter is stacked at the loca-
tion of the current stack pointer. Instruction exe-
cution begins at user patch code.
Reset Peripherals
No Operation
RST
NOP
Asserts RESET for 512 clock cycles. The CPU is
not reset by this command. Synonymous with the
CPU RESET instruction.
NOP performs no operation and may be used as
a null command.
5.10.2.5 Background Mode Registers
BDM processing uses three special purpose registers to keep track of program context
during development. A description of each follows.
MC68331
CENTRAL PROCESSING UNIT
MOTOROLA
5-21
USER’S MANUAL
MOTOROLA [ MOTOROLA ]
