INSTRUCTION
REGISTER BUS
DEVELOPMENT SYSTEM
CPU
DATA
16
16
0
RCV DATA LATCH
COMMAND LATCH
DSI
SERIAL IN
PARALLEL OUT
PARALLEL IN
SERIAL OUT
DSO
PARALLEL IN
SERIAL OUT
SERIAL IN
PARALLEL OUT
16
STATUS
RESULT LATCH
5
EXECUTION
UNIT
16
STATUS
SYNCHRONIZE
MICROSEQUENCER
M
DATA
DSCLK
CONTROL
LOGIC
CONTROL
LOGIC
SERIAL
CLOCK
32 DEBUG I/O BLOCK
Figure 5-9 Debug Serial I/O Block Diagram
The serial interface uses a full-duplex synchronous protocol similar to the serial pe-
ripheral interface (SPI) protocol. The development system serves as the master of the
serial link since it is responsible for the generation of DSCLK. If DSCLK is derived from
the CPU32 system clock, development system serial logic is unhindered by the oper-
ating frequency of the target processor. Operable frequency range of the serial clock
is from DC to one-half the processor system clock frequency.
The serial interface operates in full-duplex mode —data is transmitted and received
simultaneously by both master and slave devices. In general, data transitions occur on
the falling edge of DSCLK and are stable by the following rising edge of DSCLK. Data
is transmitted MSB first, and is latched on the rising edge of DSCLK.
The serial data word is 17 bits wide — 16 data bits and a status/control bit. Bit 16 in-
dicates the status of CPU-generated messages as shown in Table 5-6.
MC68331
CENTRAL PROCESSING UNIT
MOTOROLA
5-23
USER’S MANUAL
MOTOROLA [ MOTOROLA ]
