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MC68331CPV16 参数 Datasheet PDF下载

MC68331CPV16图片预览
型号: MC68331CPV16
PDF下载: 下载PDF文件 查看货源
内容描述: 用户手册 [User’s Manual]
分类和应用: 微控制器和处理器外围集成电路时钟
文件页数/大小: 254 页 / 1319 K
品牌: MOTOROLA [ MOTOROLA ]
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5.10.2.5.1 Fault Address Register (FAR)  
The FAR contains the address of the faulting bus cycle immediately following a bus or  
address error. This address remains available until overwritten by a subsequent bus  
cycle. Following a double bus fault, the FAR contains the address of the last bus cycle.  
The address of the first fault (if there was one) is not visible to the user.  
5.10.2.5.2 Return Program Counter (RPC)  
The RPC points to the location where fetching will commence after transition from  
background mode to normal mode. This register should be accessed to change the  
flow of a program under development. Changing the RPC to an odd value will cause  
an address error when normal mode prefetching begins.  
5.10.2.5.3 Current Instruction Program Counter (PCC)  
The PCC holds a pointer to the first word of the last instruction executed prior to tran-  
sition into background mode. Due to instruction pipelining, the instruction pointed to  
may not be the instruction which caused the transition. An example is a breakpoint on  
a released write. The bus cycle may overlap as many as two subsequent instructions  
before stalling the instruction sequencer. A breakpoint asserted during this cycle will  
not be acknowledged until the end of the instruction executing at completion of the bus  
cycle. PCC will contain $00000001 if BDM is entered via a double bus fault immedi-  
ately out of reset.  
5
5.10.2.6 Returning from BDM  
BDM is terminated when a resume execution (GO) or call user code (CALL) command  
is received. Both GO and CALL flush the instruction pipeline and refetch instructions  
from the location pointed to by the RPC.  
The return PC and the memory space referred to by the status register SUPV bit reflect  
any changes made during BDM. FREEZE is negated prior to initiating the first  
prefetch. Upon negation of FREEZE, the serial subsystem is disabled, and the signals  
revert to IPIPE/IFETCH functionality.  
5.10.2.7 Serial Interface  
Communication with the CPU32 during BDM occurs via a dedicated serial interface,  
which shares pins with other development features. Figure 5-9 is a block diagram of  
the interface. The BKPT signal becomes the serial clock (DSCLK); serial input data  
(DSI) is received on IFETCH, and serial output data (DSO) is transmitted on IPIPE.  
MOTOROLA  
5-22  
CENTRAL PROCESSING UNIT  
MC68331  
USER’S MANUAL