欢迎访问ic37.com |
会员登录 免费注册
发布采购

MC68331CPV16 参数 Datasheet PDF下载

MC68331CPV16图片预览
型号: MC68331CPV16
PDF下载: 下载PDF文件 查看货源
内容描述: 用户手册 [User’s Manual]
分类和应用: 微控制器和处理器外围集成电路时钟
文件页数/大小: 254 页 / 1319 K
品牌: MOTOROLA [ MOTOROLA ]
 浏览型号MC68331CPV16的Datasheet PDF文件第116页浏览型号MC68331CPV16的Datasheet PDF文件第117页浏览型号MC68331CPV16的Datasheet PDF文件第118页浏览型号MC68331CPV16的Datasheet PDF文件第119页浏览型号MC68331CPV16的Datasheet PDF文件第121页浏览型号MC68331CPV16的Datasheet PDF文件第122页浏览型号MC68331CPV16的Datasheet PDF文件第123页浏览型号MC68331CPV16的Datasheet PDF文件第124页  
5.10.2.2.1 External BKPT Signal  
Once enabled, BDM is initiated whenever assertion of BKPT is acknowledged. If BDM  
is disabled, a breakpoint exception (vector $0C) is acknowledged. The BKPT input has  
the same timing relationship to the data strobe trailing edge as does read cycle data.  
There is no breakpoint acknowledge bus cycle when BDM is entered.  
5.10.2.2.2 BGND Instruction  
An illegal instruction, $4AFA, is reserved for use by development tools. The CPU32  
defines $4AFA (BGND) to be a BDM entry point when BDM is enabled. If BDM is dis-  
abled, an illegal instruction trap is acknowledged.  
5.10.2.2.3 Double Bus Fault  
The CPU32 normally treats a double bus fault, or two bus faults in succession, as a  
catastrophic system error, and halts. When this condition occurs during initial system  
debug (a fault in the reset logic), further debugging is impossible until the problem is  
corrected. In BDM, the fault can be temporarily bypassed, so that the origin of the fault  
can be isolated and eliminated.  
5.10.2.2.4 Peripheral Breakpoints  
5
CPU32 peripheral breakpoints are implemented in the same way as external break-  
points — peripherals request breakpoints by asserting the BKPT signal. Consult the  
appropriate peripheral user's manual for additional details on the generation of periph-  
eral breakpoints.  
5.10.2.3 Entering BDM  
When the processor detects a breakpoint or a double bus fault, or decodes a BGND  
instruction, it suspends instruction execution and asserts the FREEZE output. This is  
the first indication that the processor has entered BDM. Once FREEZE has been as-  
serted, the CPU enables the serial communication hardware and awaits a command.  
The CPU writes a unique value indicating the source of BDM transition into temporary  
register A (ATEMP) as part of the process of entering BDM. A user can poll ATEMP  
and determine the source (see Table 5-4) by issuing a read system register command  
(RSREG). ATEMP is used in most debugger commands for temporary storage — it is  
imperative that the RSREG command be the first command issued after transition into  
BDM.  
Table 5-4 Polling the BDM Entry Source  
Source  
ATEMP[31:16]  
SSW*  
ATEMP[15:0]  
$FFFF  
Double Bus Fault  
BGND Instruction  
Hardware Breakpoint  
$0000  
$0001  
$0000  
$0000  
*Special status word (SSW) is described in detail in the CPU32 Reference Manual (CPU32RM/AD).  
A double bus fault during initial stack pointer/program counter (SP/PC) fetch sequence  
is distinguished by a value of $FFFFFFFF in the current instruction PC. At no other  
time will the processor write an odd value into this register.  
MOTOROLA  
5-20  
CENTRAL PROCESSING UNIT  
MC68331  
USER’S MANUAL